[Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0

More pruning away of features until we have a stable system and a basis for debugging what's missing. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't mix srcu tag and negative error codes (rev2)

== Series Details == Series: drm/i915: Don't mix srcu tag and negative error codes (rev2) URL : https://patchwork.freedesktop.org/series/66524/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14386_full

[Intel-gfx] [PATCH 2/9] drm/print: add drm_debug_enabled()

Add helper to check if a drm debug category is enabled. Convert drm core to use it. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_atomic_uapi.c | 2 +- drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++--- drivers/gpu/drm/drm_edid.c| 2 +-

[Intel-gfx] [PATCH 8/9] drm/amdgpu: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Cc: Alex Deucher Cc: Christian König Cc: David (ChunMing) Zhou Cc: amd-...@lists.freedesktop.org Signed-off-by: Jani Nikula --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++-- 1 file changed,

[Intel-gfx] [PATCH 1/9] drm/print: move drm_debug variable to drm_print.[ch]

Move drm_debug variable declaration and definition to where they are relevant and needed. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_drv.c | 17 - drivers/gpu/drm/drm_print.c | 19 +++ include/drm/drm_drv.h | 2 --

[Intel-gfx] [PATCH 0/9] drm/print: add and use drm_debug_enabled()

Hi all, just a little refactoring around drm_debug access to abstract it better. There shouldn't be any functional changes. I'd appreciate acks for merging the lot via drm-misc. If there are any objections to that, we'll need to postpone the last patch until everything has been merged and

[Intel-gfx] [PATCH 9/9] drm/print: rename drm_debug to __drm_debug to discourage use

drm_debug_enabled() is the way to check. __drm_debug is now reserved for drm print code only. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_print.c | 8 include/drm/drm_print.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH 6/9] drm/msm: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Cc: Rob Clark Cc: Sean Paul Cc: linux-arm-...@vger.kernel.org Cc: freedr...@lists.freedesktop.org Signed-off-by: Jani Nikula --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- 1 file changed, 2

[Intel-gfx] [PATCH 5/9] drm/i915: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 2 +-

[Intel-gfx] [PATCH 7/9] drm/nouveau: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Cc: Ben Skeggs Cc: nouv...@lists.freedesktop.org Signed-off-by: Jani Nikula --- drivers/gpu/drm/nouveau/dispnv50/disp.h | 4 ++-- drivers/gpu/drm/nouveau/nouveau_drv.h | 4 ++-- 2 files changed, 4

[Intel-gfx] [PATCH 4/9] drm/i2c/sil164: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Cc: Francisco Jerez Signed-off-by: Jani Nikula --- drivers/gpu/drm/i2c/sil164_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i2c/sil164_drv.c

[Intel-gfx] [PATCH 3/9] drm/etnaviv: use drm_debug_enabled() to check for debug categories

Allow better abstraction of the drm_debug global variable in the future. No functional changes. Cc: Lucas Stach Cc: Russell King Cc: Christian Gmeiner Cc: etna...@lists.freedesktop.org Signed-off-by: Jani Nikula --- drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 8 1 file changed, 4

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only unwedge if we can reset first

== Series Details == Series: drm/i915/gt: Only unwedge if we can reset first URL : https://patchwork.freedesktop.org/series/66637/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6887 -> Patchwork_14395 Summary ---

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only unwedge if we can reset first

Quoting Patchwork (2019-09-13 10:35:06) > == Series Details == > > Series: drm/i915/gt: Only unwedge if we can reset first > URL : https://patchwork.freedesktop.org/series/66637/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6887 -> Patchwork_14395 >

Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

Hi José, Thank you for the patch. On Thu, Sep 12, 2019 at 12:51:31PM -0700, José Roberto de Souza wrote: > This 3 non-atomic drivers all have the same function getting the > only encoder available in the connector, also atomic drivers have > this fallback. So moving it a common place and sharing

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev9)

== Series Details == Series: DC3CO Support for TGL (rev9) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Add DC3CO required register and bits Okay! Commit: drm/i915/tgl: Add DC3CO

Re: [Intel-gfx] [PATCH v3 00/37] Introduce memory region concept (including device local memory)

On Thu, 12 Sep 2019 at 23:33, Joonas Lahtinen wrote: > > Quoting Dave Airlie (2019-08-13 22:20:52) > > On Sat, 10 Aug 2019 at 08:26, Matthew Auld wrote: > > > > > > In preparation for upcoming devices with device local memory, introduce > > > the > > > concept of different memory regions, and a

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges

== Series Details == Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66638/ State : success == Summary == CI Bug Log - changes from CI_DRM_6888 -> Patchwork_14396

[Intel-gfx] ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev9)

== Series Details == Series: DC3CO Support for TGL (rev9) URL : https://patchwork.freedesktop.org/series/64923/ State : success == Summary == CI Bug Log - changes from CI_DRM_6888 -> Patchwork_14397 Summary --- **SUCCESS** No

[Intel-gfx] [PATCH v2] drm/i915: introduce INTEL_DISPLAY_ENABLED()

Prepare for making a distinction between not having display and having disabled display. Add INTEL_DISPLAY_ENABLED() and use it where HAS_DISPLAY() is used after intel_device_info_runtime_init(). This is initially duplication, as disabling display still leads to ->pipe_mask = 0 and HAS_DISPLAY()

Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

On Thu, Sep 12, 2019 at 12:51:31PM -0700, José Roberto de Souza wrote: > This 3 non-atomic drivers all have the same function getting the > only encoder available in the connector, also atomic drivers have > this fallback. So moving it a common place and sharing between atomic > and non-atomic

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev9)

== Series Details == Series: DC3CO Support for TGL (rev9) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim checkpatch origin/drm-tip c3f36fdec82d drm/i915/tgl: Add DC3CO required register and bits 0a2bd8b728de drm/i915/tgl: Add DC3CO mask to

Re: [Intel-gfx] [PATCH 2/9] drm/print: add drm_debug_enabled()

On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote: > Add helper to check if a drm debug category is enabled. Convert drm core > to use it. No functional changes. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/drm_atomic_uapi.c | 2 +- > drivers/gpu/drm/drm_dp_mst_topology.c |

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges

== Series Details == Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66638/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Introduce gen12 forcewake ranges

Re: [Intel-gfx] [PATCH v2] drm/i915: Don't mix srcu tag and negative error codes

Chris Wilson writes: > While srcu may use an integer tag, it does not exclude potential error > codes and so may overlap with our own use of -EINTR. Use a separate > outparam to store the tag, and report the error code separately. While > changing the function signature allow the caller to

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0

Chris Wilson writes: > More pruning away of features until we have a stable system and a basis > for debugging what's missing. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_pci.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

== Series Details == Series: series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66619/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14387_full

[Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0

More pruning away of features until we have a stable system and a basis for debugging what's missing. v2: Fixup vdbox/vebox fusing Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_pci.c | 1 +

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Check that we do find forcewake domain on gen11+

Quoting Mika Kuoppala (2019-09-13 15:16:52) > By always requiring a valid forcewake domain, even > FORCEWAKE_NONE, we can make assertions that accesses > need to land on a valid domain and not go out of bounds. So since we only look up restricted ranges in the fw_table, we could just have a short

Re: [Intel-gfx] [PATCH] drm/i915/gt: Only unwedge if we can reset first

Quoting Ville Syrjälä (2019-09-13 17:03:34) > On Fri, Sep 13, 2019 at 08:47:20AM +0100, Chris Wilson wrote: > > Unwedging the GPU requires a successful GPU reset before we restore the > > default submission, or else we may see residual context switch events > > that we were not expecting. > > > >

[Intel-gfx] [PATCH] drm/i915/tgl: Enable the blitter ring for basic igt support

IGT depends on the blitter for several of its basic tests, so enable it. Hopefully, this is not the straw that breaks the camel's back. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH] drm/i915: Enable stolen for iommu on snb/ivb

Now that we have CI testing of iommu, let's enable stolen + iommu with a lot more confidence that we can diagnose any potential erors. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Martin Peres --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 7 --- 1 file changed, 7 deletions(-)

[Intel-gfx] [PATCH] drm/i915/tgl: Extend MI_SEMAPHORE_WAIT

On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to update the length field and emit that extra parameter and any padding noop as required. v2: Define the token shift while we are adding the updated MI_SEMAPHORE_WAIT Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Daniele

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Enable guc logging on guc log relay write (rev2)

== Series Details == Series: drm/i915/guc: Enable guc logging on guc log relay write (rev2) URL : https://patchwork.freedesktop.org/series/66502/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14392_full

[Intel-gfx] [PATCH i-g-t] igt/gem_blits: Check for blitter support before use

Not all HW supports XY blitter commands, so check before use. In particular, this makes it easier to debug the kernel. Signed-off-by: Chris Wilson Cc: Matthew Auld --- lib/i915/gem_submission.c | 28 + lib/i915/gem_submission.h | 9

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Enable the blitter ring for basic igt support

== Series Details == Series: drm/i915/tgl: Enable the blitter ring for basic igt support URL : https://patchwork.freedesktop.org/series/66673/ State : success == Summary == CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14403 Summary

[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Verify the LRC register layout between init and HW

Before we submit the first context to HW, we need to construct a valid image of the register state. This layout is defined by the HW and should match the layout generated by HW when it saves the context image. Asserting that this should be equivalent should help avoid any undefined behaviour and

[Intel-gfx] [PATCH 1/2] drm/i915: Show the logical context ring state on dumping

Include the active context register state when dumping the engine. Suggested-by: Mika Kuoppala Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Extend MI_SEMAPHORE_WAIT

== Series Details == Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT URL : https://patchwork.freedesktop.org/series/66625/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14389_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Update Gen11 forcewake ranges

== Series Details == Series: series starting with [1/3] drm/i915: Update Gen11 forcewake ranges URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14401

Re: [Intel-gfx] [PATCH] drm/i915/gt: Only unwedge if we can reset first

On Fri, Sep 13, 2019 at 08:47:20AM +0100, Chris Wilson wrote: > Unwedging the GPU requires a successful GPU reset before we restore the > default submission, or else we may see residual context switch events > that we were not expecting. > > v2: Pull in the special-case reset_clobbers_display,

Re: [Intel-gfx] [PATCH 3/9] drm/etnaviv: use drm_debug_enabled() to check for debug categories

On Fr, 2019-09-13 at 14:51 +0300, Jani Nikula wrote: > Allow better abstraction of the drm_debug global variable in the > future. No functional changes. > > Cc: Lucas Stach > Cc: Russell King > Cc: Christian Gmeiner > Cc: etna...@lists.freedesktop.org > Signed-off-by: Jani Nikula Acked-by:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Limit ourselves to just rcs0

== Series Details == Series: drm/i915/tgl: Limit ourselves to just rcs0 URL : https://patchwork.freedesktop.org/series/66652/ State : success == Summary == CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14399 Summary ---

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display/icl: Bump up the hdisplay and vdisplay as per transcoder limits

Hey, Op 29-07-2019 om 21:17 schreef Manasi Navare: > Hi Ville, > > Thanks for your review, so do we want to merge this as is or > do we need some function to reject the 8K mode on ICL in > intel_dp_mode_valid()? > > Manasi I've pushed this series as-is because it blocks my bigjoiner work. We

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2)

== Series Details == Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2) URL : https://patchwork.freedesktop.org/series/66610/ State : warning == Summary == $ dim checkpatch origin/drm-tip 63b6a8f6a4d6 drm/i915: introduce INTEL_DISPLAY_ENABLED() -:142: WARNING:LONG_LINE: line over 100

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2)

== Series Details == Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2) URL : https://patchwork.freedesktop.org/series/66610/ State : success == Summary == CI Bug Log - changes from CI_DRM_6889 -> Patchwork_14398 Summary ---

[Intel-gfx] [PATCH 3/3] drm/i915: Check that we do find forcewake domain on gen11+

By always requiring a valid forcewake domain, even FORCEWAKE_NONE, we can make assertions that accesses need to land on a valid domain and not go out of bounds. Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c

[Intel-gfx] [PATCH 1/3] drm/i915: Update Gen11 forcewake ranges

Daniele noticed new render ranges in Gen11 fw table. Bspec: 18331 Cc: Daniele Ceraolo Spurio Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Introduce gen12 forcewake ranges

From: Michel Thierry The media ranges extend beyond what gen11 gives so we can't piggypack on gen11 ranges, even on read side. Introduce a table for gen12 and accessors for it. v2: correctly implement gen12_fwtable_write/read (Daniele) v3: update with ranges from bspec. v4: avoid

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Update Gen11 forcewake ranges

== Series Details == Series: series starting with [1/3] drm/i915: Update Gen11 forcewake ranges URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Update Gen11 forcewake ranges Okay! Commit:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Limit ourselves to just rcs0 (rev2)

== Series Details == Series: drm/i915/tgl: Limit ourselves to just rcs0 (rev2) URL : https://patchwork.freedesktop.org/series/66652/ State : success == Summary == CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14402 Summary ---

Re: [Intel-gfx] [PATCH] drm/i915: Don't unwedge if reset is disabled

On Monday, September 9, 2019 11:48:42 PM CEST Chris Wilson wrote: > Quoting Chris Wilson (2019-09-07 09:39:52) > > Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05) > > > > > > > > > On 9/5/19 2:09 AM, Janusz Krzysztofik wrote: > > > > When trying to reset a device with reset capability

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: add and use drm_debug_enabled()

== Series Details == Series: drm/print: add and use drm_debug_enabled() URL : https://patchwork.freedesktop.org/series/66656/ State : success == Summary == CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14400 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

== Series Details == Series: series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66626/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14391_full

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges

== Series Details == Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66638/ State : success == Summary == CI Bug Log - changes from CI_DRM_6888_full -> Patchwork_14396_full

Re: [Intel-gfx] [PATCH 02/14] drm/i915/tgl: TC helper function to return pin mapping

On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza wrote: > > From: "Taylor, Clinton A" > > Add a helper function to return pin map for use during dkl phy > DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it. > > The user of this function will come in future TC patches.

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/4] i915/gem_exec_balancer: Beware the migratory fence

On Sat, 7 Sep 2019 at 13:00, Chris Wilson wrote: > > If the object needs to be migrated, it may will need GPU relocs and so > have an exclusive fence showing up in the write domain. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___

[Intel-gfx] [CI 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

Make both GuC and HuC to use "." as the separator. Hardcode the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC. The current convention being: _uc_..patch.bin Update the versions of HuC being loaded of the platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev2)

== Series Details == Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev2) URL : https://patchwork.freedesktop.org/series/66625/ State : failure == Summary == Applying: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT Using index info to reconstruct a base tree... M

[Intel-gfx] [CI 2/2] HAX: force enable_guc=2

Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..f9fbb1f2fabf 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Show the logical context ring state on dumping

== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66678/ State : success == Summary == CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14405

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

== Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66685/ State : success == Summary == CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14407

[Intel-gfx] [CI] drm/i915/tgl: Re-enable rc6

From: Mika Kuoppala We think that we got rc6 problems sorted out. Flip the switch and let CI expose our tendency to naive optimism. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extracts from plane min cdclk/fp16 series

== Series Details == Series: drm/i915: Extracts from plane min cdclk/fp16 series URL : https://patchwork.freedesktop.org/series/66688/ State : success == Summary == CI Bug Log - changes from CI_DRM_6892 -> Patchwork_14408 Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable stolen for iommu on snb/ivb

== Series Details == Series: drm/i915: Enable stolen for iommu on snb/ivb URL : https://patchwork.freedesktop.org/series/66675/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14404 Summary ---

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Update Gen11 forcewake ranges

On 9/13/19 7:16 AM, Mika Kuoppala wrote: Daniele noticed new render ranges in Gen11 fw table. Bspec: 18331 Cc: Daniele Ceraolo Spurio Signed-off-by: Mika Kuoppala Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/intel_uncore.c | 23 +-- 1

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Introduce gen12 forcewake ranges

On 9/13/19 7:16 AM, Mika Kuoppala wrote: From: Michel Thierry The media ranges extend beyond what gen11 gives so we can't piggypack on gen11 ranges, even on read side. Introduce a table for gen12 and accessors for it. v2: correctly implement gen12_fwtable_write/read (Daniele) v3: update

[Intel-gfx] [PATCH 2/4] drm/i915: Allow downscale factor of <3.0 on glk+ for all formats

From: Ville Syrjälä Bspec says that glk+ max downscale factor is <3.0 for all pixel formats. Older platforms had a max of <2.0 for NV12. Update the code to deal with this. Reviewed-by: Maarten Lankhorst Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 9

[Intel-gfx] [PATCH 1/4] drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar()

From: Ville Syrjälä There's a helper in drm_fourcc.h these days to check of we're dealing with a two plane YUV format. Make use if it. Also s/plane/color_plane/ in skl_plane_relative_data_rate() to reduce the confusion. Reviewed-by: Maarten Lankhorst Signed-off-by: Ville Syrjälä ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Re-enable rc6

== Series Details == Series: drm/i915/tgl: Re-enable rc6 URL : https://patchwork.freedesktop.org/series/66689/ State : success == Summary == CI Bug Log - changes from CI_DRM_6892 -> Patchwork_14409 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Show the logical context ring state on dumping

== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66678/ State : warning == Summary == $ dim checkpatch origin/drm-tip 70695b168708 drm/i915: Show the logical context ring state on

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

== Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66685/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9f557dad9e62 drm/i915/uc: Update HuC firmware

Re: [Intel-gfx] [PATCH v7 3/7] drm: Add DisplayPort colorspace property

On Thu, Sep 12, 2019 at 02:33:34PM +0300, Gwan-gyeong Mun wrote: > Because between HDMI and DP have different colorspaces, it renames > drm_mode_create_colorspace_property() function to > drm_mode_create_hdmi_colorspace_property() function for HDMI connector. > And it adds

[Intel-gfx] [PATCH 3/4] drm/i915: Extract intel_modeset_calc_cdclk()

From: Ville Syrjälä Exfiltrate the cdclk code from intel_modeset_checks() into intel_modeset_calc_cdclk(). Reviewed-by: Maarten Lankhorst Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cdclk.c | 135 ++- drivers/gpu/drm/i915/display/intel_cdclk.h |

[Intel-gfx] [PATCH 0/4] drm/i915: Extracts from plane min cdclk/fp16 series

From: Ville Syrjälä A few reviewed patches from the plane min cdclk/fp16 series. Just feeding them to CI. Ville Syrjälä (4): drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar() drm/i915: Allow downscale factor of <3.0 on glk+ for all formats drm/i915:

[Intel-gfx] [PATCH 4/4] drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check()

From: Ville Syrjälä Clean up the mess with the drm vs. intel types in intel_crtc_atomic_check() and rename varibles accordingly. Reviewed-by: Maarten Lankhorst Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 54 ++-- 1 file changed, 26

Re: [Intel-gfx] [CI] drm/i915/tgl: Re-enable rc6

Quoting Chris Wilson (2019-09-13 21:06:38) > From: Mika Kuoppala > > We think that we got rc6 problems sorted out. Flip the switch > and let CI expose our tendency to naive optimism. > > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3)

== Series Details == Series: drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3) URL : https://patchwork.freedesktop.org/series/66551/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14393_full

[Intel-gfx] [PATCH CI 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

This 3 non-atomic drivers all have the same function getting the only encoder available in the connector, also atomic drivers have this fallback. So moving it a common place and sharing between atomic and non-atomic drivers. While at it I also removed the mention of

[Intel-gfx] [PATCH CI 2/2] drm/connector: Allow max possible encoders to attach to a connector

Currently we restrict the number of encoders that can be linked to a connector to 3, increase it to match the maximum number of encoders that can be initialized(32). To more effiently do that lets switch from an array of encoder ids to bitmask. v2: Fixing missed return on

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Enable non-power-of-2 OA report sizes

== Series Details == Series: drm/i915/perf: Enable non-power-of-2 OA report sizes URL : https://patchwork.freedesktop.org/series/66697/ State : warning == Summary == $ dim checkpatch origin/drm-tip debe3b5da38e drm/i915/perf: rework aging tail workaround -:235: CHECK:SPACING: No space is

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Enable non-power-of-2 OA report sizes

== Series Details == Series: drm/i915/perf: Enable non-power-of-2 OA report sizes URL : https://patchwork.freedesktop.org/series/66697/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894 -> Patchwork_14411 Summary ---

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake ranges

== Series Details == Series: series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66630/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14394_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

== Series Details == Series: series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66701/ State : warning == Summary == $ dim checkpatch origin/drm-tip 08e1c14ecdb6 drm/connector: Share

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

== Series Details == Series: series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66701/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

== Series Details == Series: series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66701/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894 -> Patchwork_14412

[Intel-gfx] i915 firmware updates (CMl- GuC,HuC; TGL-DMC,ICL-DMC, HuC Updates-SKL,BXT,KBL,GLK,ICL)

Hi, Kyle, Josh,Ben Ignore the previous PR and kindly consider this one. It has another new update and is the latest one- The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f: linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09 04:22:42 -0400)

Re: [Intel-gfx] [PATCH 1/4] drm/i915/tgl: Add missing ddi clock select during DP init sequence

This series was supersede by https://patchwork.freedesktop.org/series/66695/ On Wed, 2019-09-11 at 18:10 -0700, José Roberto de Souza wrote: > From: "Taylor, Clinton A" > > Step 4.b was complete missed because it is only required to TC and > TBT. > > Bspec: 49190 > Signed-off-by: Taylor,

[Intel-gfx] [PATCH 02/14] drm/i915/tgl: TC helper function to return pin mapping

From: "Taylor, Clinton A" Add a helper function to return pin map for use during dkl phy DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it. The user of this function will come in future TC patches. Signed-off-by: Taylor, Clinton A ---

[Intel-gfx] [PATCH 10/14] drm/i915/tgl: Fix dkl phy register space addressing

It was always modifing register space of the first phy in the HIP_INDEX_REG for all ports while it should shift 8 bits for each port inside of HIP_INDEX_REG. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++

[Intel-gfx] [PATCH 04/14] drm/i915/tgl: Fix driver crash when update_active_dpll is called

From: "Taylor, Clinton A" TGL PLL function table doesn't include and update_active_pll function. The driver attempts to make a call to this function and crashes during PLL changes. Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 1 file changed, 1

[Intel-gfx] [PATCH 09/14] drm/i915/icl: Unify disable and enable phy clock gating functions

Adding a enable parameters allow us to share most of the code between enable and disable functions. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 71 1 file changed, 22 insertions(+), 49 deletions(-) diff --git

[Intel-gfx] [PATCH 06/14] drm/i915/tgl: Add initial dkl pll support

From: Lucas De Marchi The disable function can be the same as for MG phy since the same registers are used. The others are different as registers changed, also adding a empty dkl_pll_write() to be implemented later. Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH 07/14] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the bspec all the registers are read modify write. Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65

[Intel-gfx] [PATCH 13/14] drm/i915/tgl: Use dkl pll hardcoded values

From: "Taylor, Clinton A" BSpec PLL calculation are not validated/ready yet, so for now it is providing a table with hardcoded values to all DP link rates. So for now lets override the calculated values with the hardcoded ones. With this hardcoded values the port clock calculation for 5.4Ghz

[Intel-gfx] [PATCH 00/14] TGL TC enabling

This is all the patches required to have TC alt-mode working on TGL, no TBT or legacy support intented here but much of the work here will help those. The dkl pll calculation is not 100% ready, so it is using the hardcoded table provided but even with this table it results in a port_clock state

[Intel-gfx] [PATCH 11/14] drm/i915/tgl: Check the UC health of tc controllers after power on

New step added for TGL, requiring for us to check the TC microcontroller health after power on TC aux. BSpec: 49294 Signed-off-by: José Roberto de Souza --- .../gpu/drm/i915/display/intel_display_power.c | 16 1 file changed, 16 insertions(+) diff --git

[Intel-gfx] [PATCH 01/14] drm/i915/tgl: Add missing ddi clock select during DP init sequence

From: "Taylor, Clinton A" Step 4.b was complete missed because it is only required to TC and TBT. Bspec: 49190 Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 08/14] drm/i915/tgl: Add dkl phy programming sequences

From: "Taylor, Clinton A" Added DKL Phy sequences and helpers functions to program voltage swing, clock gating and dp mode. It is not written in DP enabling sequence but "PHY Clockgating programming" states that clock gating should be enabled after the link training but doing so causes all the

[Intel-gfx] [PATCH 03/14] drm/i915/tgl: Finish modular FIA support on registers

If platform supports and has modular FIA is enabled, the registers bits also change, example: reading TC3 registers with modular FIA enabled, driver should read from FIA2 but with TC1 bits offsets. It is described in BSpec 50231 for DFLEXDPSP, other registers don't have the BSpec description but

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