== Series Details ==
Series: treewide: remove unused argument in lock_release()
URL : https://patchwork.freedesktop.org/series/67007/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On 9/20/19 5:51 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : failure
== Summary ==
CI Bug Log - changes from
== Series Details ==
Series: series starting with [v2,1/6] drm/i915: add i915_driver_modeset_remove()
URL : https://patchwork.freedesktop.org/series/67013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4f0318a8e293 drm/i915: add i915_driver_modeset_remove()
78b6e3b96f95
Disable rc6 to re-enable all engines. It seems that the multi-engine
machine lockup is tied to rc6; disabling it makes a gem-sync --run
basic-store-all survive for a few hours, whereas without we expect it to
die within seconds. The only question is how does CI fare with the
exchange?
For testing
Before we submit the first context to HW, we need to construct a valid
image of the register state. This layout is defined by the HW and should
match the layout generated by HW when it saves the context image.
Asserting that this should be equivalent should help avoid any undefined
behaviour and
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/67009/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46eb3a716fff drm/i915/guc: Enable guc logging on guc log
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/67009/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6929 -> Patchwork_14480
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variables to i915. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++--
The code is too specific and detailed to have open in a high level
function. Abstract away. As a drive-by improvement switch to using
enableddisabled() in logging and git rid of a redundant !!. No
functional changes.
v2: drop the !! while at it too (Chris)
Reviewed-by: Chris Wilson
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. No functional
changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 59 -
1 file changed,
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. Also propagate
to intel_hpd_poll_fini(). No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c |
The i915 specific mode config init code is too specific and detailed to
have open in a high level function. Abstract away. No functional
changes.
v2: nest drm_mode_config_init() in the function too (Chris)
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
For completeness, add counterpart to i915_driver_modeset_probe() and
remove the asymmetry in the probe/remove parts. No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 25 +++--
1 file changed, 15 insertions(+),
For completeness, add counterpart to i915_driver_modeset_probe() and
remove the asymmetry in the probe/remove parts. No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 25 +++--
1 file changed, 15 insertions(+),
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. No functional
changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 59 -
1 file changed,
On Fri, Sep 20, 2019 at 1:54 PM Lucas De Marchi
wrote:
>
> On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> wrote:
> >
> > From: Clinton A Taylor
> >
> > Add a helper function to return pin map for use during dkl phy
> > DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
>
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that clock
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/66956/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6929 ->
On Fri, 20 Sep 2019, Jani Nikula wrote:
> In general, prefer struct drm_i915_private * over struct drm_device *
> when either will do. Rename the local variables to i915. No functional
> changes.
This one was also already
Reviewed-by: Chris Wilson
in
Quoting Patchwork (2019-09-20 20:52:03)
> == Series Details ==
>
> Series: drm/i915/tgl: Swap engines for rc6/powersaving
> URL : https://patchwork.freedesktop.org/series/67010/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14482
>
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Vandita Kulkarni
>
> Add a new function to write to dkl phy pll registers. As per the
> bspec all the registers are read modify write.
>
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: José Roberto de Souza
>
Quoting Summers, Stuart (2019-09-20 22:09:46)
> On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> > On 18/09/2019 18:31, Stuart Summers wrote:
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> >
> > Unless there was some discussion I missed we can't just turn it on
>
On Fri, 2019-09-20 at 22:29 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-09-20 22:09:46)
> > On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> > > On 18/09/2019 18:31, Stuart Summers wrote:
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> > >
> > >
On Fri, 2019-09-20 at 14:44 -0700, Lucas De Marchi wrote:
> On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> wrote:
> > From: Clinton A Taylor
> >
> > Added DKL Phy sequences and helpers functions to program voltage
> > swing, clock gating and dp mode.
> >
> > It is not written in DP
> -Original Message-
> From: Chris Wilson
> Sent: Friday, September 20, 2019 9:04 AM
> To: Bloomfield, Jon ; intel-
> g...@lists.freedesktop.org; Tvrtko Ursulin
> Subject: RE: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from
> overtaking each other on preemption
>
> Quoting
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> Adding a enable parameters allow us to share most of the code between
> enable and disable functions.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 71
> 1
Disable rc6 to re-enable all engines. It seems that the multi-engine
machine lockup is tied to rc6; disabling it makes a gem-sync --run
basic-store-all survive for a few hours, whereas without we expect it to
die within seconds. The only question is how does CI fare with the
exchange?
For testing
New step added for TGL, required for us to check the TC
microcontroller health after power on TC aux.
BSpec: 49294
Reviewed-by: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +
1 file changed, 13 insertions(+)
diff
If platform supports and has modular FIA is enabled, the registers
bits also change, example: reading TC3 registers with modular FIA
enabled, driver should read from FIA2 but with TC1 bits offsets.
It is described in BSpec 50231 for DFLEXDPSP, other registers don't
have the BSpec description but
From: Clinton A Taylor
Step 4.b was complete missed because it is only required to TC and TBT.
Bspec: 49190
Reviewed-by: Imre Deak
Reviewed-by: Lucas De Marchi
Signed-off-by: Clinton A Taylor
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 -
1
Patches from https://patchwork.freedesktop.org/series/66695/#rev2
that got rv-b and don't have dependencies over other patches, for
CI testing.
Clinton A Taylor (2):
drm/i915/tgl: Add missing ddi clock select during DP init sequence
drm/i915/tgl/pll: Set update_active_dpll
José Roberto de
Adding a enable parameters allow us to share most of the code between
enable and disable functions.
v3:
Renamed icl_phy_clock_gating() to icl_phy_set_clock_gating()
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 73
From: Clinton A Taylor
Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
port is active") added this new hook while in parallel TGL upstream was
happening and this was missed.
Without this driver will crash when TC DDI is added and driver is
preparing to do a full modeset.
From: Vandita Kulkarni
These are the registers needed to program Dekel phy. Some register
definitions will be reused from MG PHY definitions, so adding a
comment on those.
Bspec: 49295
Reviewed-by: Lucas De Marchi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton A Taylor
== Series Details ==
Series: TGL TC enabling v2-CI
URL : https://patchwork.freedesktop.org/series/67022/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14485
Summary
---
**FAILURE**
Serious
Please ignore the two patches here. Critical fumble.
BR,
Jani.
On Fri, 20 Sep 2019, Jani Nikula wrote:
> For completeness, add counterpart to i915_driver_modeset_probe() and
> remove the asymmetry in the probe/remove parts. No functional changes.
>
> Reviewed-by: Chris Wilson
>
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register
layout between init and HW
URL : https://patchwork.freedesktop.org/series/67018/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b9117e29756 drm/i915/selftests: Verify the LRC
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register
layout between init and HW
URL : https://patchwork.freedesktop.org/series/67018/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14484
On Sat, Sep 21, 2019 at 01:55:25AM +0800, kbuild test robot wrote:
> tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
> head: 4bb6a9d5d9a8289673c4cb0786d44be8a63c21db
> commit: 6b97b118d4d542c7bc25b725c6de3947fffb921b [6/7] drm/i915/display:
> Extract ilk_read_luts()
>
>
== Series Details ==
Series: drm/i915/tgl: Swap engines for rc6/powersaving
URL : https://patchwork.freedesktop.org/series/67010/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14482
Summary
---
The expectation for bonded submission is that they are run concurrently,
in parallel on multiple engines. However, given a lack of constraints in
the scheduler's selection combined with timeslicing could mean that the
bonded requests could be run in opposite order on the same engine. With
just the
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/66956/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version:
== Series Details ==
Series: series starting with [v2,1/6] drm/i915: add i915_driver_modeset_remove()
URL : https://patchwork.freedesktop.org/series/67013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14483
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Add a helper function to return pin map for use during dkl phy
> DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
>
> The user of this function will come in future TC patches.
>
>
On Wed, 2019-09-18 at 13:39 -0700, Daniele Ceraolo Spurio wrote:
>
> On 9/18/19 10:31 AM, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> >
>
> What's the planned usage here? TGL HW only supports slice-level
> power-gating and with only 1 slice on TGL
On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> On 18/09/2019 18:31, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
>
> Unless there was some discussion I missed we can't just turn it on
> to
> work around a SKIP in IGT. Feature was
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 4bb6a9d5d9a8289673c4cb0786d44be8a63c21db
commit: 6b97b118d4d542c7bc25b725c6de3947fffb921b [6/7] drm/i915/display:
Extract ilk_read_luts()
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
On Thu, Jul 18, 2019 at 05:50:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I was playing around with YCbCr 4:4:4 output and noticed several
> things wrong in our code. So I fixed it all and tossed in the
> prep work for YCbCr 4:4:4 output on ilk+.
>
> Ville Syrjälä (12):
>
Quoting Patchwork (2019-09-20 22:08:48)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/selftests: Verify the LRC
> register layout between init and HW
> URL : https://patchwork.freedesktop.org/series/67018/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes
== Series Details ==
Series: TGL TC enabling v2-CI (rev2)
URL : https://patchwork.freedesktop.org/series/67022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14486
Summary
---
**SUCCESS**
No
On 20/09/2019 12:47, Anna Karas wrote:
Insert structure members names into their descriptions to follow
kernel-doc format.
Reviewed-by: Chris Wilson
Signed-off-by: Anna Karas
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
1 file
Quoting Chris Wilson (2019-09-20 09:12:54)
> Our sanitychecks indicate that while this register is context
> saved/restore, the HW does not preserve this bit within the register --
> it likely doesn't exist, or one of those mythical bits that the
> architects insist does something despite all
On Thu, 19 Sep 2019, Swati Sharma wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer)
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
== Series Details ==
Series: Revert "drm/i915/tgl: Implement Wa_1406941453"
URL : https://patchwork.freedesktop.org/series/66986/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6927 -> Patchwork_14469
Summary
---
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev9)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14464_full
Summary
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
Display State Buffer (DSB) is hardware capability which allows driver
to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
HSDES:
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Our sanitychecks indicate that while this register is context
saved/restore, the HW does not preserve this bit within the register --
it likely doesn't exist, or one of those mythical bits that the
architects insist does something despite all appearances to the
contrary.
For reference,
Mdev bus only support vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
one example is virtio-mdev[1] driver. This means we need to add device
class id support in bus match method to pair the mdev device and mdev
driver correctly.
Currently, except for the crate and remove. The rest fields of
mdev_parent_ops is just designed for vfio-mdev driver and may not help
for kernel mdev driver. So follow the device id support by previous
patch, this patch introduces device specific ops which points to
device specific ops (e.g vfio
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec 53998.
v2: Start using same icl_get_bw_info function to avoid
code duplication. Moved mpagesize to memory info
related structure as it is now dependent on
== Series Details ==
Series: DSB enablement. (rev8)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7569987ee218 drm/i915/dsb: feature flag added for display state buffer.
9c2ddae7699f drm/i915/dsb: DSB context creation.
== Series Details ==
Series: DSB enablement. (rev8)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14468
Summary
---
**SUCCESS**
No
Chris Wilson writes:
> Before we execute a batch, we must first issue any and all TLB
> invalidations so that batch picks up the new page table entries.
> Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> invalidate pipe-control and allowing the loading of the batch buffer
>
Hi all:
There are hardware that can do virtio datapath offloading while having
its own control path. This path tries to implement a mdev based
unified API to support using kernel virtio driver to drive those
devices. This is done by introducing a new mdev transport for virtio
(virtio_mdev) and
This path introduces a new mdev transport for virtio. This is used to
use kernel virtio driver to drive the mediated device that is capable
of populating virtqueue directly.
A new virtio-mdev driver will be registered to the mdev bus, when a
new virtio-mdev device is probed, it will register the
== Series Details ==
Series: drm/i915: Extract GT render sleep (rc6) management
URL : https://patchwork.freedesktop.org/series/66937/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6923_full -> Patchwork_14459_full
Summary
On Thu, Sep 19, 2019 at 2:36 PM Souza, Jose wrote:
>
> On Thu, 2019-09-19 at 14:27 -0700, Lucas De Marchi wrote:
> > On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> > wrote:
> > > Extending ICL mg calculations to also support dkl calculations.
> > >
> > > BSpec: 49204
> > >
> > >
== Series Details ==
Series: DSB enablement. (rev8)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
This patch implements basic support for mdev driver that support
virtio transport for kernel driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c | 7 ++
include/linux/mdev.h | 3 +
include/linux/virtio_mdev.h | 141 ++
3 files
This sample driver creates mdev device that simulate virtio net device
over virtio mdev transport. The device is implemented through vringh
and workqueue. A device specific dma ops is to make sure HVA is used
directly as the IOVA. This should be sufficient for kernel virtio
driver to work.
No
We want to copy from iov to buf, so the direction was wrong.
Signed-off-by: Jason Wang
---
drivers/vhost/vringh.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/vhost/vringh.c b/drivers/vhost/vringh.c
index 08ad0d1f0476..a0a2d74967ef 100644
---
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its master,
creating an implicit dependency -- if we ignore that implicit dependency
and allow
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec 53998.
v2: Start using same icl_get_bw_info function to avoid
code duplication. Moved mpagesize to memory info
related structure as it is now dependent on
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
Signed-off-by: Stanislav Lisovskiy
---
On Fri, 20 Sep 2019, Animesh Manna wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by
On Fri, 20 Sep 2019, Kai Vehmanen wrote:
> When audio power domain is suspended, the display driver must
> save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
> systems. The initial value of the register is set by BIOS and
> is read by driver during the audio component init sequence.
>
> Cc:
Quoting Mika Kuoppala (2019-09-20 09:14:36)
> Chris Wilson writes:
>
> > Before we execute a batch, we must first issue any and all TLB
> > invalidations so that batch picks up the new page table entries.
> > Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> > invalidate
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14463_full
When audio power domain is suspended, the display driver must
save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
systems. The initial value of the register is set by BIOS and
is read by driver during the audio component init sequence.
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Kai
On 19/09/2019 18:49, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-19 18:11:14)
On 19/09/2019 14:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-19 14:02:19)
On 19/09/2019 12:19, Chris Wilson wrote:
+static struct intel_timeline *get_timeline(struct i915_request *rq)
+{
+
== Series Details ==
Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations (rev2)
URL : https://patchwork.freedesktop.org/series/66703/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14461_full
Insert structure members names into their descriptions to follow
kernel-doc format.
Reviewed-by: Chris Wilson
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git
We want to program slave planes with the master plane_state for
properties such as FB, rotation, coordinates, etc, but the
slave plane_state for all programming parameters.
Instead of special casing NV12 Y-planes, we make the code more
generic, Y planes are programmed with separate state from the
Similar to plane programming, we need a separate master_plane_state from
which we will read all atomic properties, and plane_state for the real
coordinates.
Although we add all planes with icl_add_linked_planes(),
icl_check_nv12_planes() may add extra Y planes on the slave CRTC.
For those planes,
It's useful to know what the actual clipped state is, rather than
the unclipped crtc properties.
This is useful when a plane is spread across 2 crtc's, where the
slave crtc has no own plane properties but derives its clipped
values from the master crtc.
Signed-off-by: Maarten Lankhorst
---
A lot of delta, the main difference is that the master_plane_state is
not the same plane_state as being written to.
We read all properties like color key, crtc, fb, rotation from the
master_plane_state and coordinate properties.
The coordinate properties are different between the 2 bigjoiner
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
with the calculations breaking at HBR3.
As a result our calculated bpp was way too high, and the link width
limitation never came into effect.
Print out the resulting
Now that we can program planes from the update_slave callback, and
we have done all fb pinning correctly, it's time to program those
planes as well.
We use the update_slave callback as it allows us to use the
separate states correctly.
Signed-off-by: Maarten Lankhorst
---
Can't figure out how it works, so just removing it..
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c
1 - 100 of 188 matches
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