== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
805a6f5f1e23 drm/i915/tgl: Add DC3CO required register and bits
5e43f1ddfa09 drm/i915/tgl: Add DC3CO mask to
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev3)
URL : https://patchwork.freedesktop.org/series/67195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14547
On Fri, Sep 20, 2019 at 01:42:24PM +0200, Maarten Lankhorst wrote:
> Make vdsc work when no output is enabled. The big joiner needs VDSC
> on the slave, so enable it and set the appropriate bits.
> Also update timestamping constants, because slave crtc's are not
> updated in
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14548
Summary
---
**FAILURE**
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is
On 2019/9/25 下午9:21, Michael S. Tsirkin wrote:
On Wed, Sep 25, 2019 at 08:45:21PM +0800, Jason Wang wrote:
On 2019/9/25 下午5:09, Tian, Kevin wrote:
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Tuesday, September 24, 2019 9:54 PM
This patch implements basic support for mdev driver that
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO
If Local memory is supported by hardware, we want framebuffer backing
gem objects out of local memory.
If local memory is supported and gem object if not from local memory we
migrate the obj into local memory. And once framebuffer is created we
block the migration of the associated object out of
When LMEM is supported, dumb buffer preferred to be created from LMEM.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/.
v2:
Parameters are reshuffled. [Chris]
Signed-off-by: Ramalingam C
cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 18
Each GEM object is initialized with allowed memory regions for
it's migration across memory region.
In future patch we are restricting the memory regions or few objects.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/
CC: Matthew Auld
Signed-off-by:
On Thu, Sep 26, 2019 at 01:26:22AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev2)
> URL : https://patchwork.freedesktop.org/series/67195/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Fri, Sep 20, 2019 at 01:42:23PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
>
From: Gustavo Padovan
Add implementation for async plane update callbacks
Signed-off-by: Gustavo Padovan
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Tina Zhang
Signed-off-by: Helen Koike
Tested-by: Tina Zhang
---
Hi,
I ran the following tests and no regressions were found:
From: Gustavo Padovan
Replace the legacy cursor implementation by the async callbacks
Signed-off-by: Gustavo Padovan
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Helen Koike
---
Changes in v11: None
Changes in v10: None
Changes in v9:
- v8:
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific (rev2)
URL : https://patchwork.freedesktop.org/series/67195/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14545
== Series Details ==
Series: series starting with [v11,1/2] drm/i915: Introduce async plane update
to i915
URL : https://patchwork.freedesktop.org/series/67254/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14546
== Series Details ==
Series: drm/i915/huc: fix version parsing from CSS header
URL : https://patchwork.freedesktop.org/series/67248/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14541
Summary
---
== Series Details ==
Series: GuC engine reset support
URL : https://patchwork.freedesktop.org/series/67251/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14543
Summary
---
**SUCCESS**
No
From: Clinton A Taylor
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the
Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.
Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or
From: Lucas De Marchi
Now that TC support was added, initialize DDIs.
Reviewed-by: José Roberto de Souza
Acked-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
1 file changed, 6
According to the bspec, GLK/CNL have a smaller small joiner RAM buffer
than ICL+. This feels like something that could easily change again on
future platforms, so let's just add a function to return the proper
per-platform buffer size. That may also slightly simplify the upcoming
bigjoiner
TGL TC enabling v4
v1: https://patchwork.freedesktop.org/series/66695/#rev1
v2: https://patchwork.freedesktop.org/series/66695/#rev2
v2 patches merged: https://patchwork.freedesktop.org/series/67022/
v3: https://patchwork.freedesktop.org/series/66695/#rev3
v3 patches merged:
From: Clinton A Taylor
BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
now taking in consideration the pin assignment and allowing us to
optimize power by shutting down available but not needed lanes.
It was tested on ICL and TGL, with adaptors that used pin assignment
C and
Reviewed-by: Lyude Paul
On Wed, 2019-09-25 at 17:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make drm_dp_get_vc_payload() tolerate arbitrary DP_LINK_BW_*
> values, just like drm_dp_bw_code_to_link_rate() does since commit
> 57a1b0893782 ("drm: Make the bw/link rate calculations
> From: Jason Wang
> Sent: Wednesday, September 25, 2019 8:45 PM
>
>
> On 2019/9/25 下午5:09, Tian, Kevin wrote:
> >> From: Jason Wang [mailto:jasow...@redhat.com]
> >> Sent: Tuesday, September 24, 2019 9:54 PM
> >>
> >> This patch implements basic support for mdev driver that supports
> >> virtio
Another attempt at providing GuC a list of registers to
save/restore during engine resets [1].
The list we provide GuC should mirror, with possibly some exceptions,
the list of registers applied during execlists_resume/enable_execlists.
Any ideas on how to flag any discrepancies (yet flexible
== Series Details ==
Series: Panel rotation patches (rev8)
URL : https://patchwork.freedesktop.org/series/61870/
State : failure
== Summary ==
Applying: drm/panel: Add helper for reading DT rotation
Applying: drm/panel: set display info in panel attach
error: sha1 information is lacking or
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Fix dsc bpp calculations, v5.
URL : https://patchwork.freedesktop.org/series/67203/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6954_full -> Patchwork_14526_full
Reviewed-by: Lyude Paul
Cc: Mikita Lipski - figured you'd want to know ahead of time you'll need to
update your changes to drm_dp_calc_pbn_mode() to match
On Wed, 2019-09-25 at 17:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the drm_fixp_from_fraction() usage and just
== Series Details ==
Series: series starting with [01/27] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/67206/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6954_full -> Patchwork_14527_full
== Series Details ==
Series: TGL TC enabling (rev4)
URL : https://patchwork.freedesktop.org/series/66695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14544
Summary
---
**SUCCESS**
No
On Wed, 25 Sep 2019, "Saarinen, Jani" wrote:
> Hi,
>
>> -Original Message-
>> From: Intel-gfx On Behalf Of Swati
>> Sharma
>> Sent: tiistai 24. syyskuuta 2019 16.58
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; daniel.vet...@ffwll.ch; Nautiyal,
>> Ankit K
>>
>> Subject:
On Tue, 24 Sep 2019, Swati Sharma wrote:
> This reverts commit 84af7649188194a74cdd6437235a5e3c86108f0f.
>
> This is causing problems with the display, displays are all
> bright colors.
>
> Signed-off-by: Swati Sharma
Pushed, thanks for the patch.
Now we do need to figure out how to do at
> From: Jason Wang
> Sent: Tuesday, September 24, 2019 9:53 PM
>
> Mdev bus only supports vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> the first driver could be virtio-mdev. This means we need to add
> device class id
Quoting Tvrtko Ursulin (2019-09-24 16:25:29)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > @@ -449,8 +447,6 @@ tl_write(struct intel_timeline *tl, struct
> > intel_engine_cs *engine, u32 value)
> > struct i915_request *rq;
> > int err;
> >
> > -
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Tuesday, September 24, 2019 9:53 PM
>
> Hi all:
>
> There are hardware that can do virtio datapath offloading while having
> its own control path. This path tries to implement a mdev based
> unified API to support using kernel virtio driver
> From: Alex Williamson
> Sent: Wednesday, September 25, 2019 7:07 AM
>
> On Tue, 24 Sep 2019 21:53:29 +0800
> Jason Wang wrote:
>
> > Currently, except for the create and remove, the rest of
> > mdev_parent_ops is designed for vfio-mdev driver only and may not help
> > for kernel mdev driver.
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Fix dsc bpp calculations, v5.
URL : https://patchwork.freedesktop.org/series/67203/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae2d2fb87831 drm/i915/dp: Fix dsc bpp calculations, v5.
-:23:
== Series Details ==
Series: drm/i915: Small joiner RAM buffer size is platform-specific
URL : https://patchwork.freedesktop.org/series/67195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952 -> Patchwork_14525
Summary
Quoting Tvrtko Ursulin (2019-09-24 16:57:12)
>
> On 02/09/2019 05:03, Chris Wilson wrote:
> > wait_for_timelines is essentially the same loop as retiring requests
> > (with an extra), so merge the two into one routine.
>
> Extra suspense! :)
>
> >
> > Signed-off-by: Chris Wilson
> > ---
> >
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Tuesday, September 24, 2019 9:54 PM
>
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> include/linux/mdev.h| 2 +
>
On 25/09/2019 09:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-24 16:25:29)
On 02/09/2019 05:02, Chris Wilson wrote:
@@ -449,8 +447,6 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs
*engine, u32 value)
struct i915_request *rq;
int err;
-
== Series Details ==
Series: Revert "drm/i915/color: Extract icl_read_luts()"
URL : https://patchwork.freedesktop.org/series/67174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6948_full -> Patchwork_14517_full
Summary
Hey,
Op 25-09-2019 om 07:53 schreef Matt Roper:
> According to the bspec, GLK/CNL have a smaller small joiner RAM buffer
> than ICL+. This feels like something that could easily change again on
> future platforms, so let's just add a function to return the proper
> per-platform buffer size.
Quoting Tvrtko Ursulin (2019-09-23 09:10:26)
>
> On 20/09/2019 17:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
> >>
> >> On 02/09/2019 05:02, Chris Wilson wrote:
> >>> Since we cannot allocate underneath the vm->mutex (it is used in the
> >>> direct-reclaim paths), we
== Series Details ==
Series: series starting with [v2] drm/i915/selftests: Verify the LRC register
layout between init and HW (rev5)
URL : https://patchwork.freedesktop.org/series/67135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6948_full -> Patchwork_14518_full
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
with the calculations breaking at HBR3.
As a result our calculated bpp was way too high, and the link width
limitation never came into effect.
Print out the resulting
Readout the FEC state in encoder->get_config(), this will allow
us to ensure that we can correctly inherit the state from boot,
and that we set FEC during modeset.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 +
On 24/09/2019 23:01, Chris Wilson wrote:
Our semaphore time is measured by sampling a ring register, whereas our
busy time is measured exactly. This leaves a window of discrepancy that
we wish to keep small (at least within sample tolerance).
References:
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Fix dsc bpp calculations, v5.
URL : https://patchwork.freedesktop.org/series/67203/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6954 -> Patchwork_14526
On 02/09/2019 05:03, Chris Wilson wrote:
As our global unpark/park keep track of the number of active users, we
can simply move the accounting from the GEM layer to the base GT layer.
It was placed originally inside GEM to benefit from the 100ms extra
delay on idleness, but that has been
On Wed, Sep 25, 2019 at 10:21:09AM +0200, Maarten Lankhorst wrote:
> There was a integer wraparound when mode_clock became too high,
> and we didn't correct for the FEC overhead factor when dividing,
> with the calculations breaking at HBR3.
>
> As a result our calculated bpp was way too high,
Quoting Chris Wilson (2019-09-25 12:24:08)
> Quoting Chris Wilson (2019-09-25 12:17:14)
> > Quoting Tvrtko Ursulin (2019-09-25 11:57:53)
> > >
> > > I am still slightly uneasy about having requests, which I see as a GEM
> > > concept, be retired from GT, but okay, it's not the most important
On 2019/9/25 上午7:06, Alex Williamson wrote:
> On Tue, 24 Sep 2019 21:53:29 +0800
> Jason Wang wrote:
>
>> Currently, except for the create and remove, the rest of
>> mdev_parent_ops is designed for vfio-mdev driver only and may not help
>> for kernel mdev driver. With the help of class id, this
Quoting Tvrtko Ursulin (2019-09-25 13:41:10)
> [+ Daniele, I think he might want to have a look at this.]
>
> On 25/09/2019 11:01, Chris Wilson wrote:
> > With the introduction of ctx->engines[] we allow multiple logical
> > contexts to be used on the same engine (e.g. with virtual engines). Each
On 25/09/2019 11:01, Chris Wilson wrote:
struct_mutex provides no serialisation of the registers and data
structures being saved and restored across suspend/resume. It is
completely superfluous here.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_suspend.c | 8
1 file
On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate
> them
> differently than ICL. While we're moving it, fix up the ICL
> translation
> for LPDDR4.
>
> BSpec: 53998
>
> v2: Fix up ICL LPDDR4 entry (Ville); Drop unused
On Wed, Sep 25, 2019 at 02:59:02AM +0300, Souza, Jose wrote:
> On Tue, 2019-09-24 at 18:58 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 12:55:11PM -0700, José Roberto de Souza
> > wrote:
> > > Link training is failling when running link at 2.7GHz and 1.62GHz
> > > and
> > > following BSpec
Hi Chris,
On Wed, Sep 25, 2019 at 02:08:45PM +0100, Chris Wilson wrote:
> Having decided that we only care about the promotion predicate, we can
> simplify gen12_csb_parse to simply check whether we need to jump to a
> new queue.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc:
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 14 +-
1 file changed, 5
From: Ville Syrjälä
We depend on a specific relationship between the VIC number and the
index in the CEA mode arrays. Assert that the arrays have the excpected
size to make sure we've not accidentally left holes in them.
v2: Pimp the BUILD_BUG_ON()s
Cc: Hans Verkuil
Cc: Shashank Sharma
From: Ville Syrjälä
We're going to need two cea mode tables (on for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] to indicathe how it's to be
indexed.
Cc: Hans Verkuil
Cc:
From: Ville Syrjälä
Get rid of the drm_fixp_from_fraction() usage and just do the
straightforward calculation directly.
Cc: Lyude Paul
Cc: Harry Wentland
Cc: Alex Deucher
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_mst_topology.c | 18 ++
1 file changed, 2
From: Ville Syrjälä
Remainder of the new CTA-861-G modes. I already pushed the first patch
adding the modes with VIC<128. I did improve the BUILD_BUG_ON()s in the
last patch a bit to make it easier to visually double check the numbers
against VIC comments in the mode arrays.
Ville Syrjälä (4):
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 151 -
1 file changed, 149 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Make drm_dp_get_vc_payload() tolerate arbitrary DP_LINK_BW_*
values, just like drm_dp_bw_code_to_link_rate() does since commit
57a1b0893782 ("drm: Make the bw/link rate calculations more forgiving").
Cc: Lyude Paul
Cc: Sean Paul
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Replace the nested ifs with a single if and a logical AND.
Cc: Lyude Paul
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_mst_topology.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
Quoting Patchwork (2019-09-25 16:17:59)
> == Series Details ==
>
> Series: drm/i915/tgl: Swap rps disable for rc6 disable
> URL : https://patchwork.freedesktop.org/series/67214/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14529
>
On Wed, Sep 25, 2019 at 08:45:21PM +0800, Jason Wang wrote:
>
> On 2019/9/25 下午5:09, Tian, Kevin wrote:
> > > From: Jason Wang [mailto:jasow...@redhat.com]
> > > Sent: Tuesday, September 24, 2019 9:54 PM
> > >
> > > This patch implements basic support for mdev driver that supports
> > > virtio
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev3)
URL : https://patchwork.freedesktop.org/series/66993/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
04ff25dfcc58 drm/i915: Restrict qgv points which don't have enough
On Wed, Sep 25, 2019 at 04:18:09PM +0200, Maarten Lankhorst wrote:
> Op 25-09-2019 om 15:01 schreef Ville Syrjälä:
> > On Fri, Sep 20, 2019 at 01:42:17PM +0200, Maarten Lankhorst wrote:
> >> Now that we separated everything into uapi and hw, it's
> >> time to make the split definitive. Remove the
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev3)
URL : https://patchwork.freedesktop.org/series/66993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14528
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952_full ->
Op 25-09-2019 om 15:01 schreef Ville Syrjälä:
> On Fri, Sep 20, 2019 at 01:42:17PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>>
On Wed, Sep 25, 2019 at 02:21:52AM +0300, Souza, Jose wrote:
> On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> > > On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> > > wrote:
> > > > [...]
> > > > +
On 25/09/2019 13:51, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-25 13:41:10)
[+ Daniele, I think he might want to have a look at this.]
On 25/09/2019 11:01, Chris Wilson wrote:
With the introduction of ctx->engines[] we allow multiple logical
contexts to be used on the same engine
Hi Ville,
I have revised the patch from DRM_ERROR to DRM_DEBUG, could you please review?
https://patchwork.freedesktop.org/patch/332806/?series=66837=3
Thanks,
-Original Message-
From: S, Srinivasan
Sent: Thursday, September 19, 2019 7:22 PM
To: 'Ville Syrjälä'
Cc: Navare, Manasi D ;
== Series Details ==
Series: drm/i915/tgl: Swap rps disable for rc6 disable
URL : https://patchwork.freedesktop.org/series/67214/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956 -> Patchwork_14529
Summary
---
On 25/09/2019 12:33, Chris Wilson wrote:
Quoting Chris Wilson (2019-09-25 12:29:40)
Quoting Chris Wilson (2019-09-25 12:24:08)
Quoting Chris Wilson (2019-09-25 12:17:14)
Quoting Tvrtko Ursulin (2019-09-25 11:57:53)
I am still slightly uneasy about having requests, which I see as a GEM
Still searching for the sweetspot to leave CI alive as we figure out the
root cause.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Acked-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c
Sanity test existing persistence and new exciting non-persistent context
behaviour.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
---
lib/i915/gem_context.c | 37
lib/i915/gem_context.h | 8 +
lib/igt_dummyload.c
Update to commit fef476f3ab47527a00818ddaf4b46b8c0936 (not upstream!)
Author: Chris Wilson
Date: Mon Aug 5 22:55:44 2019 +0100
drm/i915: Cancel non-persistent contexts on close
for I915_CONTEXT_PARAM_PERSISTENCE
---
include/drm-uapi/i915_drm.h | 22 --
1 file
Op 25-09-2019 om 06:17 schreef Matt Roper:
> On Fri, Sep 20, 2019 at 01:42:19PM +0200, Maarten Lankhorst wrote:
>> This can all be done from the intel_update_crtc function. Split out the
>> pipe update into a separate function, just like is done for the planes.
>>
>> Signed-off-by: Maarten
Op 25-09-2019 om 15:01 schreef Ville Syrjälä:
> On Fri, Sep 20, 2019 at 01:42:17PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>>
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Pull in all the changes done during fastset as well. It makes no sense
for it to still exist as a separate function.
Changes since v1:
- Inline
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead. Look at uapi/hw where appropriate.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
> This can all be done from the intel_update_crtc function. Split out the
> pipe update into a separate function, just like is done for the planes.
> Pull in all the changes done during fastset as well. It makes no sense
> for it
On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate
> > them
> > differently than ICL. While we're moving it, fix up the ICL
> > translation
> > for LPDDR4.
Op 25-09-2019 om 01:41 schreef Matt Roper:
> On Fri, Sep 20, 2019 at 01:42:17PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>> Color
== Series Details ==
Series: series starting with [01/27] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/67206/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: dma-fence: Serialise
On Wed, Sep 25, 2019 at 12:34:17PM +0200, Maarten Lankhorst wrote:
> Op 25-09-2019 om 12:26 schreef Ville Syrjälä:
> > On Wed, Sep 25, 2019 at 10:21:09AM +0200, Maarten Lankhorst wrote:
> >> There was a integer wraparound when mode_clock became too high,
> >> and we didn't correct for the FEC
On 2019/9/25 上午7:06, Alex Williamson wrote:
> On Tue, 24 Sep 2019 21:53:26 +0800
> Jason Wang wrote:
>
>> Mdev bus only supports vfio driver right now, so it doesn't implement
>> match method. But in the future, we may add drivers other than vfio,
>> the first driver could be virtio-mdev. This
On 2019/9/25 下午5:09, Tian, Kevin wrote:
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Tuesday, September 24, 2019 9:54 PM
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
include/linux/mdev.h
On 25/09/2019 11:01, Chris Wilson wrote:
We no longer need struct_mutex to serialise request emission, so remove
it from the gt selftests.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 15 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 -
On 25/09/2019 11:01, Chris Wilson wrote:
We no longer need to placate lockdep by holding struct_mutex for our
initialisation, so don't.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 --
drivers/gpu/drm/i915/i915_gem.c | 9 -
Our semaphore time is measured by sampling a ring register, whereas our
busy time is measured exactly. This leaves a window of discrepancy that
we wish to keep small (at least within sample tolerance).
v2: Explain the sema <= busy assert, and lots of other Tvrtko tweaks
References:
On Tue, Sep 24, 2019 at 10:59:57AM -0700, Manasi Navare wrote:
> On Tue, Sep 24, 2019 at 05:38:00PM +0200, Maarten Lankhorst wrote:
> > Op 22-09-2019 om 19:08 schreef Manasi Navare:
> > > After the state is committed, we readout the HW registers and compare
> > > the HW state with the SW state
1 - 100 of 222 matches
Mail list logo
