On Fri, Sep 20, 2019 at 07:06:27PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 19, 2019 at 10:53:03PM +0300, Gwan-gyeong Mun wrote:
> > Support for HDR10 video was introduced in DisplayPort 1.4.
> > On GLK+ platform, in order to use DisplayPort HDR10, we need to support
> > BT.2020 colorimetry and
Hi Chris,
On Thu, Oct 03, 2019 at 04:23:02PM +0100, Chris Wilson wrote:
> For fast preempt-resets, error capture is skipped, so disable
> preempt-resets before checking the error state. While thinking ahead, be
> prepared for when the modparams are not accessible.
>
> Signed-off-by: Chris Wilson
== Series Details ==
Series: series starting with [1/7] drm/i915: Expose engine properties via sysfs
URL : https://patchwork.freedesktop.org/series/68022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7094 -> Patchwork_14810
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
drivers/gpu/drm/i915/intel_pm.c
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Stanislav Lisovskiy (2):
On 15-Oct-19 6:04 PM, Ville Syrjälä wrote:
On Thu, Oct 10, 2019 at 04:20:04PM +0530, Sharma, Swati2 wrote:
On 09-Oct-19 7:46 PM, Ville Syrjälä wrote:
On Wed, Oct 09, 2019 at 12:25:41PM +0530, Swati Sharma wrote:
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> Configure the transcoder to operate in TE GATE command mode
> and take TE events from GPIO.
> Also disable the periodic command mode, that GOP would have
> programmed.
>
> Signed-off-by: Vandita Kulkarni
> ---
>
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev4)
URL : https://patchwork.freedesktop.org/series/67992/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
af8d69d10bd5 drm/i915: Introduce Jasper Lake PCH
-:30: WARNING:BAD_SIGN_OFF: Duplicate signature
#30:
== Series Details ==
Series: drm/i915/icl: Wa_1607087056
URL : https://patchwork.freedesktop.org/series/68036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14814
Summary
---
**SUCCESS**
No
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> From: Madhav Chauhan
>
> This patch adds a helper function to find encoder
> if DSI is operating in command mode. This function
> will be used while enabling/disabling TE interrupts
> for DSI.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by:
From: Ville Syrjälä
Move the initial setup of state->min_cdclk[]/min_voltage_level[]
into intel_modeset_calc_cdclk() alongside the rest of the global
cdclk state. And the counterparts we move into
intel_cdclk_swap_state().
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Move the min_cdclk[] and min_voltage_level[] arrays under the
rest of the cdclk state. And while at it provide a simple
helper (intel_cdclk_clear_state()) to clear the state during
the ww_mutex backoff dance.
Signed-off-by: Ville Syrjälä
---
From: Mika Kuoppala
Avoid possible hang in CPSS unit.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-6-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c
From: Mika Kuoppala
To avoid possible hang, we need to add depth stall if we flush the
depth cache.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-8-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
We are going to need this macro on limiting
the workaround scope.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-1-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
From: Mika Kuoppala
Avoid possible cs hang with semaphores by disabling
lite restore.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-11-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-7-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.
References: HSDES#1606700617
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
From: Mika Kuoppala
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
v2: use IS_TGL_REVID (Chris)
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
From: Mika Kuoppala
Avoid possible deadlock on context switch.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-9-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
Disable semaphore idle messages and wait for event
power downs.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-10-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154411.9984-1-mika.kuopp...@linux.intel.com
---
From: Mika Kuoppala
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
v2: Flush also in breadcrumbs (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
== Series Details ==
Series: drm/i915: Fix MST oops due to MSA changes
URL : https://patchwork.freedesktop.org/series/68053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14819
Summary
---
On Sun, 13 Oct 2019 13:53:59 +0800
Changbin Du wrote:
> The 'functions' directive is not only for functions, but also works for
> structs/unions. So the name is misleading. This patch renames it to
> 'specific', so now we have export/internal/specific directives to limit
> the functions/types to
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> Transcoder timing calculation differ for command mode.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 56 +-
> 1 file changed, 37 insertions(+), 19 deletions(-)
>
> diff --git
From: Ville Syrjälä
The MSA MISC computation now depends on the connector state, and
we do it from the DDI .pre_enable() hook. All that is fine for
DP SST but with MST we don't actually pass the connector state
to the dig port's .pre_enable() hook which leads to an oops.
Need to think more how
On Mon, Oct 14, 2019 at 1:51 PM Daniel Vetter wrote:
>
> On Mon, Oct 14, 2019 at 6:21 PM Li, Juston wrote:
> >
> > On Wed, 2019-10-09 at 17:50 +0200, Daniel Vetter wrote:
> > > On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > > > From: Daniel Stone
> > > >
> > > > getfb2 allows us
On Tue, Oct 15, 2019 at 11:37:17AM +0800, Jason Wang wrote:
>
> On 2019/10/15 上午1:49, Stefan Hajnoczi wrote:
> > On Fri, Oct 11, 2019 at 04:15:50PM +0800, Jason Wang wrote:
> > > There are hardware that can do virtio datapath offloading while having
> > > its own control path. This path tries to
== Series Details ==
Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
URL : https://patchwork.freedesktop.org/series/63373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d780d2521e9c drm/i915: Add debugs to distingiush a cd2x update from a full
cdclk pll
== Series Details ==
Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
URL : https://patchwork.freedesktop.org/series/63373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14821
Summary
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev4)
URL : https://patchwork.freedesktop.org/series/67992/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14822
Summary
---
On Tue, Oct 15, 2019 at 09:40:28AM -0700, Lucas De Marchi wrote:
> This way it's easier to figure out what didn't match when we have
> multiple pipes enabled.
>
> v2: pass drm_crtc and use the more common [CRTC:%d:%s] format
> (Ville)
>
> Signed-off-by: Lucas De Marchi
> ---
>
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev3)
URL : https://patchwork.freedesktop.org/series/67992/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
47be6f8097ac drm/i915: Introduce Jasper Lake PCH
-:30: WARNING:BAD_SIGN_OFF: Duplicate signature
#30:
On Tue, Oct 15, 2019 at 06:54:02PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Don't forget to set TC long detect function
> URL : https://patchwork.freedesktop.org/series/68038/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7098 ->
== Series Details ==
Series: drm/i915/execlists: Clear semaphore immediately upon ELSP promotion
(rev2)
URL : https://patchwork.freedesktop.org/series/67955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7093_full -> Patchwork_14807_full
== Series Details ==
Series: Small fixes before fixing MST (rev2)
URL : https://patchwork.freedesktop.org/series/67883/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14818
Summary
---
**FAILURE**
Depends on ummerged kernel code for getfb2
Rest of drm.h taken from:
commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c
Author: Linus Torvalds
Date: Mon Sep 30 10:35:40 2019 -0700
Linux 5.4-rc1
Signed-off-by: Juston Li
---
include/drm-uapi/drm.h | 39
From: Daniel Stone
Mirroring addfb2, add tests for the new ioctl which will return us
information about framebuffers containing multiple buffers, as well as
modifiers.
Changes since v1:
- Add test that uses getfb2 output to call addfb2 as suggested by Ville
Signed-off-by: Daniel Stone
== Series Details ==
Series: drm/i915/selftests: Drop stale struct_mutex
URL : https://patchwork.freedesktop.org/series/68011/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7093_full -> Patchwork_14806_full
Summary
---
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev3)
URL : https://patchwork.freedesktop.org/series/67992/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14817
Summary
---
== Series Details ==
Series: drm/i915/ehl: Don't forget to set TC long detect function (rev2)
URL : https://patchwork.freedesktop.org/series/68038/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14820
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
v2: Flush also in breadcrumbs (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 -
2 files
Avoid possible deadlock on context switch.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
Disable semaphore idle messages and wait for event
power downs.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git
We are going to need this macro on limiting
the workaround scope.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c46b339064c0..f6aee1e01a7f 100644
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
248cbaf741d0 drm/i915: Refactor intel_can_enable_sagv
-:33: WARNING:SUSPECT_CODE_INDENT: suspect code indent for
On Tue, 15 Oct 2019 20:17:01 +0800
Jason Wang wrote:
> On 2019/10/15 下午6:41, Cornelia Huck wrote:
> > On Fri, 11 Oct 2019 16:15:54 +0800
> > Jason Wang wrote:
> >
> >> Currently, except for the create and remove, the rest of
> >> mdev_parent_ops is designed for vfio-mdev driver only and may
From: Ville Syrjälä
So far we've sort of protected the global state under dev_priv with
the connection_mutex. I wan to change that so that we can change the
cdclk even for pure plane updates. To that end let's formalize the
protection of the global state to follow what I started with the cdclk
From: Ville Syrjälä
Various pixel formats and plane scaling impose additional constraints
on the cdclk frequency. Provide a new plane->min_cdclk() hook that
will be used to compute the minimum acceptable cdclk frequency for
each plane.
Annoyingly on some platforms the numer of active planes
From: Ville Syrjälä
Now that the planes declare their minimum cdclk requirements properly
we don't need to check the cdclk in skl_max_scale() anymore. Just check
against the maximum downscale ratio, and move the code next to it's
only caller.
v2: Add a comment explaining the HQ vs. not thing
From: Ville Syrjälä
check_digital_port_conflicts() is done needlessly late. Move it earlier.
This will be needed as later on we want to set any_ms=true a bit later
for non-modesets too and we can't call this guy without the
connection_mutex held.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Several patches have been pushed, new patches have appeared at the end.
I wonder if I've invented a perpetual motion patch series...
The new stuff is mostly just cleaning up the cdclk state (mis)management
we have going on. I also modifier the global state locking stuff
a
From: Ville Syrjälä
skl+ supports fp16 pixel formats on all universal planes. Add the
necessary bits to expose that capability. The main different to
icl is that we can't scale fp16, so need to add the relevant
checks.
v2: Rebase on top of icl fp16
Split skl+ bits into a separate patch
From: Ville Syrjälä
snb supports fp16 pixel formats on the sprite planes. Expose that
capability. Nothing special needs to be done, it just works.
v2: Rebase on top of icl fp16
Split snb+ sprite bits into a separate patch
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
ivb+ supports fp16 pixel formats on the sprite planes planes. Expose
that capability.
On ivb/hsw fp16 scanout is slightly busted. The output from the plane
will have 1/4 the expected value. For the sprite plane we can fix that
up with the plane gamma unit. This was fixed on
From: Ville Syrjälä
gen4+ supports fp16 pixel formats on the primary planes. Add the
relevant code.
On ivb fp16 scanout is slightly busted. The output from the plane will
have 1/4 the expected value. For the primary plane we would have to
use the pipe gamma or pipe csc to correct that which
From: Ville Syrjälä
Encapsulate the cdclk state handling a bit better by performing
the copy from dev_priv->cdclk into the current intel_atomic_state
within the cdclk code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++
From: Ville Syrjälä
The normal cdclk handling now takes care of making sure the
plane's pixel rate doesn't exceed the spec appointed percentage
of the cdclk frequency. Thus we can nuke
skl_check_pipe_max_pixel_rate().
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
To make the logs a bit less confusing let's toss in some
debug prints to indicate whether the cdclk reprogramming
is going to happen with a single pipe active or whether we
need to turn all pipes off for the duration.
Signed-off-by: Ville Syrjälä
---
== Series Details ==
Series: Small fixes before fixing MST (rev2)
URL : https://patchwork.freedesktop.org/series/67883/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dd2c2adfc049 drm/i915: simplify setting of ddi_io_power_domain
7d4e878c74b2 drm/i915: fix port checks for MST
On Tue, Oct 15, 2019 at 07:42:03PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Introduce Jasper Lake PCH (rev3)
> URL : https://patchwork.freedesktop.org/series/67992/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14817
>
== Series Details ==
Series: series starting with [01/11] drm/i915/tgl: Add IS_TGL_REVID
URL : https://patchwork.freedesktop.org/series/68037/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On Tue, Oct 15, 2019 at 09:40:26AM -0700, Lucas De Marchi wrote:
> Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
> connections except DDI A. Tiger Lake (gen 12) supports on all external
> connections.
>
> Move the check to happen inside intel_dp_mst_encoder_init() and add
>
== Series Details ==
Series: drm/i915/ehl: Don't forget to set TC long detect function
URL : https://patchwork.freedesktop.org/series/68038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14816
Summary
On 15/10/2019 14:26, Chris Wilson wrote:
If the system is being slow and userspace is racing ahead of the GPU and
finds itself waiting for the GPU to catch up, before the process sleeps
give the tasklet a kick, bypassing ksoftirqd. If the system is
overloaded, then ksoftirqd may be delayed
Quoting Mika Kuoppala (2019-10-15 16:44:46)
> To avoid possible hang, we need to add depth stall if we flush the
> depth cache.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
== Series Details ==
Series: drm/i915: Flush tasklet submission before sleeping on i915_request_wait
URL : https://patchwork.freedesktop.org/series/68024/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7096 -> Patchwork_14811
The Jasper Lake PCH follows ICP/TGP's south display behavior and is
identical to MCC graphics-wise except that it does not use the unusual
(port C -> TC1) pin mapping that MCC does.
Also, it turns out the extra PCH ID that we had previously thought was a
form of MCC is actually a second ID for
Instead of the ever growing switch, just compute the ddi io power domain
based on the port number.
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-2-lucas.demar...@intel.com
---
https://patchwork.freedesktop.org/series/67883/
v2:
- remove "drm/i915: cleanup unused returns on DP-MST": we should
actually care more about the error handling here - left for later
- handle other comments on the series
Lucas De Marchi (5):
drm/i915: simplify setting of
Quoting Seba Kerckhof (2019-10-15 15:37:50)
> I was experiencing tearing on my Debian system. I read about the intel driver
> "TearFree" option and configured it as explained here: https://
> wiki.archlinux.org/index.php/Intel_graphics#Tearing
>
> While it does seem to help with the tearing, it
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7096 -> Patchwork_14812
Summary
---
**SUCCESS**
No
Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
connections except DDI A. Tiger Lake (gen 12) supports on all external
connections.
Move the check to happen inside intel_dp_mst_encoder_init() and add
specific platform checks.
v2: Replace != with == checks for ports on gen <
This way it's easier to figure out what didn't match when we have
multiple pipes enabled.
v2: pass drm_crtc and use the more common [CRTC:%d:%s] format
(Ville)
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++-
1 file changed, 19
The new line is already added by pipe_config_mismatch(), so the callers
shouldn't add it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-5-lucas.demar...@intel.com
---
s/?/:/ so it gets correctly colored by dmesg.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-7-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1
On Tue, 15 Oct 2019 09:28:54 -0700
Matt Roper wrote:
> The Jasper Lake PCH follows ICP/TGP's south display behavior and is
> identical to MCC graphics-wise except that it does not use the unusual
> (port C -> TC1) pin mapping that MCC does.
>
> Also, it turns out the extra PCH ID that we had
On Tue, Oct 15, 2019 at 07:34:00PM +0530, Sharma, Swati2 wrote:
> On 15-Oct-19 6:04 PM, Ville Syrjälä wrote:
> > On Thu, Oct 10, 2019 at 04:20:04PM +0530, Sharma, Swati2 wrote:
> >> On 09-Oct-19 7:46 PM, Ville Syrjälä wrote:
> >>> On Wed, Oct 09, 2019 at 12:25:41PM +0530, Swati Sharma wrote:
>
Quoting Mika Kuoppala (2019-10-15 16:44:11)
> Avoid possible hang in tsg,vfe units by keeping
> l3 clocks runnings.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 7
Quoting Mika Kuoppala (2019-10-15 16:44:43)
> To ensure correct state data for compute workloads, we
> need to keep the ff dop clock enabled.
>
> References: HSDES#1606700617
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 -
>
Quoting Mika Kuoppala (2019-10-15 16:44:49)
> Avoid possible cs hang with semaphores by disabling
> lite restore.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>
== Series Details ==
Series: drm/i915: Move the cursor rotation handling into
intel_cursor_check_surface()
URL : https://patchwork.freedesktop.org/series/68035/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14813
From: Ville Syrjälä
Unlike other planes the cursor currently handles 180 degree rotation
adjustment during the hardware programming phase. Let's move that
stuff into intel_cursor_check_surface() to match how we do things
with other plane types.
And while at we'll plop in the final src x/y
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
-
+drivers/gpu/drm/i915/intel_pm.c:3753:6: warning:
Quoting Mika Kuoppala (2019-10-15 16:44:45)
> Avoid possible hang in tsg,vfe units by keeping
> l3 clocks runnings.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git
Quoting Mika Kuoppala (2019-10-15 16:44:44)
> Avoid possible hang in CPSS unit.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git
Quoting Mika Kuoppala (2019-10-15 16:44:39)
> We are going to need this macro on limiting
> the workaround scope.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
Since EHL's MCC PCH reuses one of the TC pins we need to supply a TC
long detect function when handling the interrupts.
Fixes: 53448aed7b80 ("drm/i915/ehl: Port C's hotplug interrupt is associated
with TC1 bits")
Reported-by: kbuild test robot
Reported-by: Dan Carpenter
Cc: Vivek Kasireddy
On Fri, 11 Oct 2019 16:15:51 +0800
Jason Wang wrote:
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index b558d4cfd082..724e9b9841d8 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -45,6 +45,12 @@ void
I was experiencing tearing on my Debian system. I read about the intel
driver "TearFree" option and configured it as explained here:
https://wiki.archlinux.org/index.php/Intel_graphics#Tearing
While it does seem to help with the tearing, it changes my detected
screens. By this I mean if I run
To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.
References: HSDES#1606700617
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9
To avoid possible hang, we need to add depth stall if we flush the
depth cache.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
v2: use IS_TGL_REVID (Chris)
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20
1 file changed, 20
Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
Avoid possible hang in CPSS unit.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
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