On 08/09/2021 21:23, Matt Roper wrote:
On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote:
On 07/09/2021 18:19, Matt Roper wrote:
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an
== Series Details ==
Series: series starting with [1/4] drm/i915: rename debugfs_gt files (rev2)
URL : https://patchwork.freedesktop.org/series/94489/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
432bfa5f078a drm/i915: rename debugfs_gt files
-:168: WARNING:FILE_PATH_CHANGES:
Op 09-09-2021 om 10:22 schreef Peter Zijlstra:
> On Thu, Sep 09, 2021 at 07:38:06AM +0200, Maarten Lankhorst wrote:
>
>>> You'll need a similar hunk in ww_rt_mutex.c
>> What tree has that file?
> Linus' tree should have it. Per commit:
>
> f8635d509d80 ("locking/ww_mutex: Implement rtmutex based
== Series Details ==
Series: series starting with [1/4] drm/i915: rename debugfs_gt files (rev2)
URL : https://patchwork.freedesktop.org/series/94489/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_20998
On Thu, Sep 09, 2021 at 07:38:06AM +0200, Maarten Lankhorst wrote:
> > You'll need a similar hunk in ww_rt_mutex.c
>
> What tree has that file?
Linus' tree should have it. Per commit:
f8635d509d80 ("locking/ww_mutex: Implement rtmutex based ww_mutex API
functions")
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Dave
> Airlie
> Sent: torstai 9. syyskuuta 2021 4.53
> To: intel-gfx@lists.freedesktop.org
> Cc: jani.nik...@linux.intel.com
> Subject: [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable
> (v3)
>
> (v3 just adds
I dont see any issues except a couple of nits.
Reviewed-by : Alan Previn
...alan
On Fri, 2021-08-27 at 18:27 -0700, Daniele Ceraolo Spurio wrote:
> 2 debugfs files, one to query the current status of the pxp session and one
> to trigger an invalidation for testing.
>
> Signed-off-by: Daniele
On 08/09/2021 18:06, Daniel Vetter wrote:
On Thu, Sep 02, 2021 at 04:01:40PM +0100, Tvrtko Ursulin wrote:
On 02/09/2021 15:33, Daniel Vetter wrote:
On Tue, Aug 31, 2021 at 02:18:15PM +0100, Tvrtko Ursulin wrote:
On 31/08/2021 13:43, Daniel Vetter wrote:
On Tue, Aug 31, 2021 at 10:15:03AM
drm-misc-next-fixes-2021-09-09:
drm-misc-next-fixes for v5.15:
- Make some dma-buf config options depend on DMA_SHARED_BUFFER.
- Handle multiplication overflow of fbdev xres/yres in the core.
The following changes since commit efcefc7127290e7e9fa98dea029163ad8eda8fb3:
drm/ttm: Fix
On Thu, Sep 9, 2021 at 5:35 AM Dave Airlie wrote:
>
> On Thu, 9 Sept 2021 at 03:44, Thomas Zimmermann wrote:
> >
> > Hi Dave and Daniel,
> >
> > here's this week's PR for drm-misc-fixes. One patch is a potential deadlock
> > in TTM, the other enables an additional plane in kmb. I'm slightly
On 2021-08-30 at 21:11:29 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev8)
> URL : https://patchwork.freedesktop.org/series/93570/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10537_full -> Patchwork_20921_full
On Thu, 09 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This moves one wrapper from the pm->display side, and creates
> wrappers for all the others, this should simplify things later.
>
> One thing to note is that the code checks the existance of some
> of these ptrs, so the wrappers are
== Series Details ==
Series: series starting with [1/4] drm/i915: rename debugfs_gt files (rev2)
URL : https://patchwork.freedesktop.org/series/94489/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_20998_full
== Series Details ==
Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/93122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_21000_full
On Thu, Sep 09, 2021 at 05:39:26PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 09, 2021 at 07:29:33AM -0700, Matt Roper wrote:
> > On Thu, Sep 09, 2021 at 04:58:50PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 07, 2021 at 11:19:29AM -0700, Matt Roper wrote:
> > > > On Tue, Sep 07, 2021 at
On Thu, Sep 09, 2021 at 08:00:02AM -0700, Matt Roper wrote:
> On Thu, Sep 09, 2021 at 05:39:26PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 09, 2021 at 07:29:33AM -0700, Matt Roper wrote:
> > > On Thu, Sep 09, 2021 at 04:58:50PM +0300, Ville Syrjälä wrote:
> > > > On Tue, Sep 07, 2021 at
== Series Details ==
Series: Enable GuC submission by default on DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/93325/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b2951b760586 drm/i915: Do not define vma on stack
60923cb16879 drm/i915/guc: put all guc objects in
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev3)
URL : https://patchwork.freedesktop.org/series/93800/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_21002_full
Summary
== Series Details ==
Series: Enable GuC submission by default on DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/93325/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev3)
URL : https://patchwork.freedesktop.org/series/93800/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
On Tue, Sep 07, 2021 at 11:19:29AM -0700, Matt Roper wrote:
> On Tue, Sep 07, 2021 at 08:41:06PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 07, 2021 at 10:27:28AM -0700, Matt Roper wrote:
> > > On Tue, Sep 07, 2021 at 10:46:39PM +0530, Ayaz A Siddiqui wrote:
> > > > MOCS table of TGL/RKL has
On 08/09/2021 18:38, Daniel Vetter wrote:
On Fri, Sep 03, 2021 at 12:24:05PM +0100, Matthew Auld wrote:
Currently we blow up in trace_dma_fence_init, when calling into
get_driver_name or get_timeline_name, since both the engine and context
might be NULL(or contain some garbage address) in the
I thought I remembered an issue with this but looked up the previous emails,
and it looks like that this change actually should be safe!
Signed-off-by: Lyude Paul
On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
> Extend the use of extended receiver cap at 0x2200 to cover
>
On Thu, Sep 09, 2021 at 06:40:59AM +1000, Dave Airlie wrote:
> On Wed, 8 Sept 2021 at 19:33, Jani Nikula wrote:
> >
> > On Wed, 08 Sep 2021, Dave Airlie wrote:
> > > From: Dave Airlie
> > >
> > > A vague goal is to have the vfunc table be the api between
> > > wm and display, not having
On Thu, Sep 09, 2021 at 04:58:50PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 07, 2021 at 11:19:29AM -0700, Matt Roper wrote:
> > On Tue, Sep 07, 2021 at 08:41:06PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 07, 2021 at 10:27:28AM -0700, Matt Roper wrote:
> > > > On Tue, Sep 07, 2021 at
On Thu, Sep 09, 2021 at 12:44:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> appears majority of performance regressions reported with an enabled
…whoops, that was supposed to be:
Reviewed-by: Lyude Paul
On Thu, 2021-09-09 at 12:18 -0400, Lyude Paul wrote:
> I thought I remembered an issue with this but looked up the previous emails,
> and it looks like that this change actually should be safe!
>
> Signed-off-by: Lyude Paul
>
> On
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev3)
URL : https://patchwork.freedesktop.org/series/93800/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3665dc8b3d2 drm/dp: add DP 2.0 UHBR link rate and bw code conversions
68ec9d98ee90 drm/dp: use more
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev3)
URL : https://patchwork.freedesktop.org/series/93800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21002
Summary
---
On Thu, Sep 09, 2021 at 07:29:33AM -0700, Matt Roper wrote:
> On Thu, Sep 09, 2021 at 04:58:50PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 07, 2021 at 11:19:29AM -0700, Matt Roper wrote:
> > > On Tue, Sep 07, 2021 at 08:41:06PM +0300, Ville Syrjälä wrote:
> > > > On Tue, Sep 07, 2021 at
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev6)
URL : https://patchwork.freedesktop.org/series/90503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21001
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev6)
URL : https://patchwork.freedesktop.org/series/90503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_21001_full
Summary
---
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata.
This api allow user mode to create protected buffers and to mark
contexts as making use of such objects. Only when using contexts
marked in such a way is the execution guaranteed to work as expected.
Contexts can only be marked as using protected content at creation time
(i.e. the parameter is
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in async flip too.
v3:
- Removed the black pixels logic for async flip. [Ville]
- Used plane state to force black pixels.
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
session state might still be marked as alive after resume. Therefore,
we should consider the session as dead on suspend and invalidate all the
2 debugfs files, one to query the current status of the pxp session and one
to trigger an invalidation for testing.
v2: rename debugfs, fix date (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by : Alan Previn
---
drivers/gpu/drm/i915/Makefile| 1 +
Now that all the pieces are in place we can add a description of how the
feature works. Also modify the comments in struct intel_pxp into
kerneldoc.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Rodrigo Vivi
---
Documentation/gpu/i915.rst | 8
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation.
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in
The setting is required by hardware to allow us doing further protection
operation such as sending commands to GPU or TEE. The register needs to
be re-programmed on resume, so for simplicitly we bundle the programming
with the component binding, which is automatically called on resume.
Further HW
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
Since the
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
v3: rename pinned_context functions (Chris)
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
v3: wait for mei PXP component to be bound.
v4: drop the wait, as the
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by:
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev6)
URL : https://patchwork.freedesktop.org/series/90503/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev6)
URL : https://patchwork.freedesktop.org/series/90503/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./include/uapi/drm/i915_drm.h:1876: warning: This comment starts with '/**',
but isn't a
Set the DP 2.0 128b/132b channel encoding for UHBR rates.
v2: Fix UHBR port clock check, use intel_dp_is_uhbr()
Bspec: 54128
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 -
1 file changed, 16 insertions(+), 1
128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.
v2:
- Use HAS_DP20 abstraction for
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++
1 file changed, 11 insertions(+)
diff
Helpful abstraction to avoid duplication.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
v2: Use intel_dp_is_uhbr
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
Let's abstract the DP 2.0 feature. Initially just DG2.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37c1ca266bcd..14416bd789b6 100644
---
UHBR rates and 128b/132b channel encoding go hand in hand.
v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville)
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++-
1 file changed, 2 insertions(+), 1
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++-
.../drm/i915/display/intel_dp_link_training.c | 86
Hi Ville,
> > > > ef79d62b5ce5 ("drm/i915: Encapsulate dbuf state handling harder")
> > > >
> > > > With that commit the display is not detected anymore, one commit
> > > > before that it still works. So this one seems to be broken.
> > > >
> > > > Ville, Stanislav, any idea how to fix this?
>
PXP (Protected Xe Path) is an i915 component, available on
GEN12+, that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
The main change from v7 is that we no longer increase the guilty count
when a context is banned
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
v2: rename the component struct (Rodrigo)
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
v2: flip kconfig default to N. Some machines have IFWIs that do not
support PXP, so we need it to be an opt-in until we add support to query
the caps from the mei device.
Signed-off-by: Daniele Ceraolo Spurio
v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks
and the already merged patches obviously dropped.
Jani Nikula (13):
drm/dp: add DP 2.0 UHBR link rate and bw code conversions
drm/dp: use more of the extended receiver cap
drm/dp: add LTTPR DP 2.0 DPCD addresses
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++
include/drm/drm_dp_helper.h | 2 ++
2 files
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++
1 file changed, 22
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc:
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register
conflicts with FDI. Since we have to deal with both meanings in the same
code, for different platforms, clarify the macro name so we don't
forget.
Bspec: 50493
Signed-off-by: Jani Nikula
---
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets just do that.
To
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev6)
URL : https://patchwork.freedesktop.org/series/90503/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4b04867d778d drm/i915/pxp: Define PXP component interface
-:31: WARNING:FILE_PATH_CHANGES: added, moved or
== Series Details ==
Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/93122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21000
== Series Details ==
Series: kernel/locking: Add context to ww_mutex_trylock. (rev2)
URL : https://patchwork.freedesktop.org/series/94437/
State : failure
== Summary ==
Patch is empty.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am
On 9/9/2021 1:17 AM, Teres Alexis, Alan Previn wrote:
I dont see any issues except a couple of nits.
Reviewed-by : Alan Previn
...alan
On Fri, 2021-08-27 at 18:27 -0700, Daniele Ceraolo Spurio wrote:
2 debugfs files, one to query the current status of the pxp session and one
to trigger
== Series Details ==
Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/93122/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
50ce004fa7ce drm/i915: Use Transparent Hugepages when IOMMU is enabled
-:6:
On Thu, Sep 02, 2021 at 05:53:32PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Implement support for fetching the hardware description table from the
> GuC. The call is made twice - once without a destination buffer to
> query the size and then a second time to fill in the
If the context is reset as a result of the request cancellation the
context reset G2H is received after schedule disable done G2H which is
the wrong order. The schedule disable done G2H release the waiting
request cancellation code which resubmits the context. This races
with the context reset G2H
Daniel Vetter pointed out that locking in the GuC submission code was
overly complicated, let's clean this up a bit before introducing more
features in the GuC submission backend.
Also fix some CI failures, port fixes from our internal tree, and add a
few more selftests for coverage.
Lastly, add
When unwinding requests on a reset context, if other requests in the
context are in the priority list the requests could be resubmitted out
of seqno order. Traverse the list of active requests in reverse and
append to the head of the priority list to fix this.
Fixes: eb5e7da736f3 ("drm/i915/guc:
Don't drop ce->guc_active.lock when unwinding a context after reset.
At one point we had to drop this because of a lock inversion but that is
no longer the case. It is much safer to hold the lock so let's do that.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Before we did some clever tricks to not use the a lock when touching
guc_state.sched_state in certain cases. Don't do that, enforce the use
of the lock.
v2:
(kernel test robo )
- Add __maybe_unused to sched_state_is_init()
v3: rebase after the unused code path removal has been moved to an
Prior to this patch the blocked context counter was cleared on
init_sched_state (used during registering a context & resets) which is
incorrect. This state needs to be persistent or the counter can read the
incorrect value resulting in scheduling never getting enabled again.
Fixes: 62eaf0ae217d
Rather than processing 1 G2H at a time and re-queuing the work queue if
more messages exist, process all the G2H in a single pass of the work
queue.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Michal Wajdeczko
---
== Series Details ==
Series: Enable GuC submission by default on DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/93325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21003
Summary
---
== Series Details ==
Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev11)
URL : https://patchwork.freedesktop.org/series/93704/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
deb17f151cef drm/i915/guc: Fix blocked context accounting
7b4cd4d6bb36
== Series Details ==
Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev11)
URL : https://patchwork.freedesktop.org/series/93704/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev11)
URL : https://patchwork.freedesktop.org/series/93704/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21004
On Thu, Sep 09, 2021 at 08:42:15PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 09, 2021 at 10:15:56AM -0700, Matt Roper wrote:
> > On Thu, Sep 09, 2021 at 06:09:55PM +0300, Ville Syrjälä wrote:
> > > On Thu, Sep 09, 2021 at 08:00:02AM -0700, Matt Roper wrote:
> > > > On Thu, Sep 09, 2021 at
On Thu, Sep 02, 2021 at 05:53:33PM -0700, john.c.harri...@intel.com wrote:
> From: Rodrigo Vivi
>
> GuC contains a consolidated table with a bunch of information about the
> current device.
>
> Previously, this information was spread and hardcoded to all the components
> including GuC, i915 and
== Series Details ==
Series: Enable GuC submission by default on DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/93325/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_21003_full
Summary
Move guc_blocked fence to struct guc_state as the lock which protects
the fence lives there.
s/ce->guc_blocked/ce->guc_state.blocked/g
v2:
(Daniele)
- s/blocked_fence/blocked/g
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c
Now that we have locking hierarchy of sched_engine->lock ->
ce->guc_state everything from guc_active can be moved into guc_state and
protected the guc_state.lock.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_context.c | 10 +--
Drop pin count check trick between a sched_disable and re-pin, now rely
on the lock and counter of the number of committed requests to determine
if scheduling should be disabled on the context.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
v3:
- Fixup a few kernel doc comments (Daniele)
v4 (Daniele):
- Implement doc suggestions from John
- Add kerneldoc
Move GuC management fields in context under guc_active struct as this is
where the lock that protects theses fields lives. Also only set guc_prio
field once during context init.
v2:
(Daniele)
- set CONTEXT_SET_INIT
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
A subsequent patch will flip the locking hierarchy from
ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
ce->guc_state.lock. As such we need to release the submit fence for a
request from an IRQ to break a lock inversion - i.e. the fence must be
release went holding
To make ownership of locking clear move fields (guc_id, guc_id_ref,
guc_id_link) to sub structure guc_id in intel_context.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context_types.h
Lock the xarray and take ref to the context if needed.
v2:
(Checkpatch)
- Add new line after declaration
(Daniel Vetter)
- Correct put / get accounting in xa_for_loops
v3:
(Checkpatch)
- Extra new line
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
While debugging an issue with full GT resets I went down a rabbit hole
thinking the scrubbing of lost G2H wasn't working correctly. This proved
to be incorrect as this was working just fine but this chase inspired me
to write a selftest to prove that this works. This simple selftest
injects errors
Rework and simplify the locking with GuC subission. Drop
sched_state_no_lock and move all fields under the guc_state.sched_state
and protect all these fields with guc_state.lock . This requires
changing the locking hierarchy from guc_state.lock -> sched_engine.lock
to sched_engine.lock ->
A context can get destroyed after cancelling a request, if a context or
GT reset occurs, so take a reference to context when cancelling a
request.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
Kick tasklet after queuing a request so it submitted in a timely manner.
Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new
inteface")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
1 file
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