Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the performance, as recommended
by HW team.
Stanislav Lisovskiy (4):
drm/i915: Pass plane to watermark calculation functions
drm/i915: Introduce do_async_flip flag to intel_plane_state
drm/i915: Use wm0
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane struct to those
functions.
v2: Pass plane instead of plane_id
v3: Do not pass plane to skl_cursor_allocation(Ville Syrjälä)
v4: - Make
There might be various logical contructs when we might want
to enable async flip, so lets calculate those and set this
flag, so that there is no need in long conditions in other
places.
v2: - Set do_async_flip flag to False, if no async flip needed.
Lets not rely that it will be
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
v2: - Removed redundant
On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prdouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
drivers/gpu/drm/i915/i915_vma_resource.c:381:9:
On Mon, Jan 24, 2022 at 11:06:52AM +0200, Stanislav Lisovskiy wrote:
> This optimization allows to achieve higher perfomance
> during async flips.
> For the first async flip we have to still temporarily
> switch to sync flip, in order to reprogram plane
> watermarks, so this requires taking into
Hi
Am 24.01.22 um 02:08 schrieb Andi Shyti:
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prdouces the following error:
'produces'
drivers/gpu/drm/i915/i915_vma_resource.c: In function
On Mon, Jan 24, 2022 at 11:11:14AM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 11:06:52AM +0200, Stanislav Lisovskiy wrote:
> > This optimization allows to achieve higher perfomance
> > during async flips.
> > For the first async flip we have to still temporarily
> > switch to sync flip,
On Mon, Jan 24, 2022 at 11:16:36AM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > v2: - Extracted min ddb async flip check to separate
== Series Details ==
Series: drm/i915: fix header file inclusion for might_alloc() (rev2)
URL : https://patchwork.freedesktop.org/series/99215/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22075
Summary
On Fri, Dec 17, 2021 at 08:52:53AM +, Wang, Zhi A wrote:
> Sorry for the late reply as I am supporting the customers recently. I
> will refresh this after the christmas.
Did you find some time to look into it? Do you want some help?
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed
== Series Details ==
Series: Async flip optimization for DG2 (rev5)
URL : https://patchwork.freedesktop.org/series/98981/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22076
Summary
---
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prdouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
drivers/gpu/drm/i915/i915_vma_resource.c:381:9:
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prodouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
Hi Christoph and Jason:
Have been talking with Raj. I am going to work on this series this week.
Thanks,
Zhi.
-Original Message-
From: Christoph Hellwig
Sent: Monday, January 24, 2022 11:40 AM
To: Wang, Zhi A
Cc: Christoph Hellwig ; Zhi Wang ;
intel-gfx@lists.freedesktop.org;
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22077
== Series Details ==
Series: Async flip optimization for DG2 (rev5)
URL : https://patchwork.freedesktop.org/series/98981/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58dc909288f9 drm/i915: Pass plane to watermark calculation functions
a8601bc34503 drm/i915: Introduce
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
145b0a01b8e8 drm/i915/snps: convert to drm device based logging
c0ed446aaf38
Op 24-01-2022 om 10:44 schreef Andi Shyti:
> Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
> as the first is not required, while the second, if not included,
> prodouces the following error:
>
> drivers/gpu/drm/i915/i915_vma_resource.c: In function
>
Sorry for spamming! Just called the command from the history
On Mon, Jan 24, 2022 at 11:42:43AM +0200, Andi Shyti wrote:
> Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
> as the first is not required, while the second, if not included,
> prdouces the following error:
>
>
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
v2: - Removed redundant
On Mon, Jan 24, 2022 at 11:51:23AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false
Op 12-01-2022 om 09:51 schreef Jani Nikula:
> We already have the gem/i915_gem_domain.c file.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c| 4 +++-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 5
Instead of calling the debug operation directly.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
---
drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
It's a reoccurring pattern that we need to extract the fence
from a dma_fence_chain object. Add a helper for this.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-fence-chain.c | 6 ++
include/linux/dma-fence-chain.h | 15 +++
2 files changed, 17 insertions(+), 4
Drivers should not add containers as shared fences to the dma_resv
object, instead each fence should be added individually.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c | 5 +
1 file changed, 5 insertions(+)
diff --git
When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a
separate swap gem object is created to hold the contents of the CCS block.
It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it
should've begun its life in lmem.
It also handles destruction of the swap bo
It's not allowed to nest another dma_fence container into a dma_fence_array
or otherwise we can run into recursion.
Warn about that when we create a dma_fence_array.
v2: fix comment style and typo in the warning pointed out by Thomas
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
i915_pmu_cpu_online() calls cpumask_weight() to check if any bit of a
given cpumask is set. We can do it more efficiently with cpumask_empty()
because cpumask_empty() stops traversing the cpumask as soon as it finds
first set bit, while cpumask_weight() counts all bits unconditionally.
It has to be used by other files other than low-level migration code.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 5 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
Instead of calling the debug operation directly.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Consolidate the wrapper functions to check for dma_fence
subclasses in the dma_fence header.
This makes it easier to document and also check the different
requirements for fence containers in the subclasses.
Signed-off-by: Christian König
---
include/linux/dma-fence-array.h | 15 +
When a flat-CCS aware bo is evicted from lmem, its control surface will be
written out into smem. This will be done in the shape of a kernel-only bo
attached to the original bo.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 10 ++
1 file changed,
Instead of manually extracting the fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index
The static array page_count is read-only so it make sense to make
it const.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c
On Fri, 21 Jan 2022, Lucas De Marchi wrote:
> On Fri, Jan 21, 2022 at 03:29:57PM +0200, Jani Nikula wrote:
>>In general, we should avoid redefining kernel macros like this. It can
>>get confusing, and what gets used will depend on whether the header is
>>included or not. Moreover, we should
On Fri, 21 Jan 2022, Matthew Brost wrote:
> On Fri, Jan 21, 2022 at 09:28:46AM +0200, Jani Nikula wrote:
>> On Thu, 20 Jan 2022, Matthew Brost wrote:
>> > Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is
>> > set, before CT write / read as this could result in a read across
Instead of manually messing with the data structures use the iterators
and extraction helpers provided by the framework.
This whole handling should essentially go away when boost handling is
implemented in the core dma-buf framework.
Signed-off-by: Christian König
---
Because the smem-evicted bo that holds the CCS block has to be blitted
separately from the original compressed bo, two sets of PTEs have to
be emitted for every bo copy.
This commit is partially based off another commit from Ramalingam C
, currently under discussion.
Signed-off-by: Adrian
Am 24.01.22 um 02:54 schrieb ira.we...@intel.com:
From: Ira Weiny
Changes from V1:
Use memcpy_to_page() where appropriate
Rebased to latest
The kmap() call may cause issues with work being done with persistent memory.
For this and other reasons it is being deprecated.
I'm
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
-
Adds frame buffer support code for flat-CCS devices, like DG2. A flat-CCS
modifier is attached to a fb object that contains the original bo by means
of the drmModeAddFB2WithModifiers drm API call.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/display/intel_fb.c | 36
Hi guys,
as previously discussed only dma_fence_chain with its previous fence is
actually made to build up larger dma_fence structures. Everything else should
either flatten all fences into a single dma_fence_array or just add each fence
separately to the dma_resv object.
Please review and/or
Since i915_gem_create_context() function return error pointers,
the kernel_context() function does not return null, It returns error
pointers too. Using IS_ERR() to check the return value to fix this.
Signed-off-by: Miaoqian Lin
---
Changes in v2:
- clean up unneeded initialization of err.
---
This series is a first attempt at handling the eviction of flat-CCS
compressed lmem-placed bo's.
The official specification of flat CCS behaviour dictates that:
"Flat CCS data needs to be cleared when a lmem object is allocated. And CCS
data can be copied in and out of CCS region through
Decomposing fence containers don't seem to make any sense here.
So just remove the function entirely and call dma_fence_wait() directly.
Signed-off-by: Christian König
Cc: VMware Graphics
Cc: Zack Rusin
---
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +-
Chaining of dma_fence_chain objects is only allowed through the prev
fence and not through the contained fence.
Warn about that when we create a dma_fence_chain.
v2: fix comment style
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Reviewed-by: Thomas Hellström
---
Smatch detected a divide by zero bug in check_overlay_scaling().
drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling()
error: potential divide by zero bug '/ rec->dst_height'.
drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling()
error:
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22077_full
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221] WARN_ON(debug_locks &&
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed
On Fri, 21 Jan 2022, Ville Syrjälä wrote:
> On Fri, Jan 21, 2022 at 03:00:29PM +0200, Jani Nikula wrote:
>> Purge some accumulated drm device based logging changes from my local
>> branches.
>>
>> Jani Nikula (9):
>> drm/i915/snps: convert to drm device based logging
>> drm/i915/pps: convert
Add request cancel trace point guarded by
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINT.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.h | 1 +
drivers/gpu/drm/i915/i915_trace.h | 10 ++
2 files changed, 11 insertions(+)
diff --git
Change the preemption timeout to the smallest possible value (1 us) when
disabling scheduling to cancel a request and restore it after
cancellation. This not only cancels the request as fast as possible, it
fixes a bug where the preemption timeout is 0 which results in the
schedule disable hanging
More than 1 request can be submitted to a single ELSP at a time if
multiple requests are ready run to on the same context. When a request
is canceled it is marked bad, an idle pulse is triggered to the engine
(high priority kernel request), the execlists scheduler sees that
running request is bad
Fix request cancellation + add request cancel low level trace point.
v2:
- Update cancel reset selftest preemption timeout value to zero
- Fix bug in execlists cancel code
Signed-off-by: Matthew Brost
Matthew Brost (4):
drm/i915: Add request cancel low level trace point
drm/i915/guc:
Set the preemption timeout to zero to prove that request cancellation
with preemption disabled works. Also this seals a race between a
possible preemption and request cancellation.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/selftests/i915_request.c | 7 ---
1 file changed, 4
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote:
> Decomposing fence containers don't seem to make any sense here.
>
> So just remove the function entirely and call dma_fence_wait()
> directly.
>
> Signed-off-by: Christian König
> Cc: VMware Graphics
> Cc: Zack Rusin
Looks good.
On 1/24/22 14:02, Maarten Lankhorst wrote:
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221]
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> It has to be used by other files other than low-level migration code.
Maybe, but i915_drv.h is not the dumping ground for this
stuff. Especially you shouldn't add anything in i915_drv.h that requires
you to pull in other headers. The goal is to go in
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> Because the smem-evicted bo that holds the CCS block has to be blitted
> separately from the original compressed bo, two sets of PTEs have to
> be emitted for every bo copy.
>
> This commit is partially based off another commit from Ramalingam C
> ,
On Sun, Jan 23, 2022 at 05:54:05PM -0800, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> kmap() is being deprecated and these instances are easy to convert to
> kmap_local_page().
>
> Furthermore, in gma_crtc_cursor_set() use the memcpy_from_page() helper
> instead of an open coded use of
Am 24.01.22 um 17:36 schrieb Thomas Hellström (Intel):
On 1/24/22 14:03, Christian König wrote:
Drivers should not add containers as shared fences to the dma_resv
object, instead each fence should be added individually.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Am 24.01.22 um 17:33 schrieb Thomas Hellström:
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote:
Instead of calling the debug operation directly.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
The first two patches seem unrelated to the series.
No idea what happened here,
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote:
> Instead of calling the debug operation directly.
>
> Signed-off-by: Christian König
> Reviewed-by: Huang Rui
The first two patches seem unrelated to the series. Also is there a
chance of a series cover-letter?
Thanks,
Thomas
> ---
== Series Details ==
Series: drm/i915/overlay: Prevent divide by zero bugs in scaling
URL : https://patchwork.freedesktop.org/series/99242/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11128 -> Patchwork_22079
Summary
On Mon, 2022-01-24 at 17:24 +0100, Thomas Hellström wrote:
> Hi, Adrian
>
> On 1/21/22 23:22, Adrian Larumbe wrote:
> > When a flat-CCS lmem-bound BO is evicted onto smem for the first
> > time, a
> > separate swap gem object is created to hold the contents of the CCS
> > block.
> > It is assumed
On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false
Internal feedback is to exactly match the register dumps
output as it did in execlist, however it seems that the
register dump function in execlist targetting the GT subsystem
also includes non-GT registers like display-related ones that
GuC doesn't manage. So for that, I will have to break up
== Series Details ==
Series: drm/i915: Lock dpt_obj around set_cache_level.
URL : https://patchwork.freedesktop.org/series/99245/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f8d0f6b03553 drm/i915: Lock dpt_obj around set_cache_level.
-:8: WARNING:COMMIT_LOG_LONG_LINE:
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote:
> It's not allowed to nest another dma_fence container into a
> dma_fence_array
> or otherwise we can run into recursion.
>
> Warn about that when we create a dma_fence_array.
>
> v2: fix comment style and typo in the warning pointed out
== Series Details ==
Series: drm/i915: fix header file inclusion for might_alloc() (rev4)
URL : https://patchwork.freedesktop.org/series/99215/
State : failure
== Summary ==
Applying: drm/i915: fix header file inclusion for might_alloc()
Using index info to reconstruct a base tree...
M
From: Ville Syrjälä
Use DISPLAY_VER rather than GRAPHICS_VER to determine
availability of display hardware features.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git
From: Ville Syrjälä
Complete the ilk pch modeset abstraction by adding ilk_pch_pre_enable().
I did the disable vs. post_disable split already for the disable
sequence, but the enable sequence was still left with the naked
ilk_fdi_pll_enable() call for some reason.
Signed-off-by: Ville Syrjälä
On 1/24/22 14:03, Christian König wrote:
Drivers should not add containers as shared fences to the dma_resv
object, instead each fence should be added individually.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Reviewed-by: Thomas Hellström
Is there any indication that this
This makes sense given the other patches in your series, but it seems as
yet no one has anything to say about this. I don't have anything
specific to comment on other than it seems to make the correct changes
to komeda given the rest.
Reviewed-by: Carsten Haitzler
On 1/11/22 10:18, Kandpal,
== Series Details ==
Series: drm/i915: Lock dpt_obj around set_cache_level.
URL : https://patchwork.freedesktop.org/series/99245/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22080
Summary
---
Hi, Adrian
On 1/21/22 23:22, Adrian Larumbe wrote:
When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a
separate swap gem object is created to hold the contents of the CCS block.
It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it
should've begun its life
On 1/24/22 14:03, Christian König wrote:
It's a reoccurring pattern that we need to extract the fence
from a dma_fence_chain object. Add a helper for this.
Signed-off-by: Christian König
Reviewed-by: Thomas Hellström
---
drivers/dma-buf/dma-fence-chain.c | 6 ++
On Sun, Jan 23, 2022 at 11:33:55PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Add Wa_18018781329 (rev7)
> URL : https://patchwork.freedesktop.org/series/99128/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11120_full ->
On Mon, Jan 24, 2022 at 01:08:26PM +0100, Christian König wrote:
> Am 24.01.22 um 02:54 schrieb ira.we...@intel.com:
> > From: Ira Weiny
> >
> > Changes from V1:
> > Use memcpy_to_page() where appropriate
> > Rebased to latest
> >
> > The kmap() call may cause issues with work being
From: Ville Syrjälä
Tryingf to do readout when we don't even have a cpu transcoder
is not a great idea. Don't do it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
We can simplify the icl check in intel_dsc_source_support()
by noting that the only case when DSC is not supported is when
using transcoder A.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +--
1 file changed,
From: Ville Syrjälä
Specify which device we're talking about when spewing
bigjoiner debugs.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git
From: Ville Syrjälä
Lift the dsc/joiner enable up from the wonky places where it
currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
into hsw_crtc_enable() where we write the other per-pipe stuff
as well. Makes the transcoder vs. pipe split less confusing.
Signed-off-by: Ville
From: Ville Syrjälä
Pull the transcoder specific modeset steps into a single place.
With bigoiner we need to keep in mind wheher we're dealing with
the transcoder or the pipe, and a slightly higher level split makes
that easier.
Signed-off-by: Ville Syrjälä
---
== Series Details ==
Series: drm/edid: Support type 7 timings
URL : https://patchwork.freedesktop.org/series/99250/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22082_full
Summary
---
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22094
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where
appropriate
URL : https://patchwork.freedesktop.org/series/99278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22089_full
On Tue, Jan 25, 2022 at 08:50:47AM +0200, Jani Nikula wrote:
> On Tue, 25 Jan 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Lift the dsc/joiner enable up from the wonky places where it
> > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> > into
== Series Details ==
Series: Fix up request cancel (rev3)
URL : https://patchwork.freedesktop.org/series/99173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11130 -> Patchwork_22095
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/selftests: make static read-only array page_count const
URL : https://patchwork.freedesktop.org/series/99252/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22085_full
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Lift the dsc/joiner enable up from the wonky places where it
> currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> into hsw_crtc_enable() where we write the other per-pipe stuff
> as well. Makes the transcoder
On Mon, 24 Jan 2022, Umesh Nerlige Ramappa
wrote:
> All timestamps returned by GuC for GuC PMU busyness are captured from
> GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle,
> kmd uses RING_TIMESTAMP to measure busyness of an engine with an active
> context. In further
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use DISPLAY_VER rather than GRAPHICS_VER to determine
> availability of display hardware features.
>
> Signed-off-by: Ville Syrjälä
On both patches,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 18
== Series Details ==
Series: Fix up request cancel (rev3)
URL : https://patchwork.freedesktop.org/series/99173/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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