== Series Details ==
Series: drm/i915/dsi: add payload receiving code (rev3)
URL : https://patchwork.freedesktop.org/series/105096/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11763 -> Patchwork_105096v3
Summary
---
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
As an extension of the current skip TLB invalidations,
check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Don't allow two engines to be reset in parallel, as they would both
try to select a reset bit (and send requests to common registers)
and wait on that register, at the same time. Serialize control of
the reset requests/acks
Hi Dave & Daniel -
drm-intel-fixes-2022-06-16:
drm/i915 fixes for v5.19-rc3:
- Fix page fault on error state read
- Fix memory leaks in per-gt sysfs
- Fix multiple fence handling
- Remove accidental static from a local variable
BR,
Jani.
The following changes since commit
On 15/06/2022 17:14, Ye, Tony wrote:
On 6/15/2022 3:13 AM, Tvrtko Ursulin wrote:
On 15/06/2022 00:15, Ye, Tony wrote:
On 6/14/2022 8:30 AM, Ceraolo Spurio, Daniele wrote:
On 6/14/2022 12:44 AM, Tvrtko Ursulin wrote:
On 13/06/2022 19:13, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 10:39
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.
Fixes:
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2022-06-16:
Two fixes for TTM, one for a NULL pointer dereference and one to make sure
the buffer is pinned prior to a bulk move, and a fix for a spurious
compiler warning.
The following changes since commit
== Series Details ==
Series: i915: Extract, polish, and document multicast handling
URL : https://patchwork.freedesktop.org/series/105134/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11758_full -> Patchwork_105134v1_full
== Series Details ==
Series: Get dsc optimal output bpp
URL : https://patchwork.freedesktop.org/series/105200/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11763_full -> Patchwork_105200v1_full
Summary
---
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Don't flush TLBs when the buffer is only used in the GGTT under full
control of the kernel, as there's no risk of of concurrent access
and stale access from prefetch.
We only need to invalidate the TLB if they are
On 5/25/22 20:43, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture.
On 5/25/22 20:43, Matthew Auld wrote:
Userspace wants to know the size of CPU visible portion of device
local-memory, and on small BAR devices the probed_size is no longer
enough. In Vulkan, for example, it would like to know the size in bytes
for CPU visible VkMemoryHeap. We already track the
From: Tvrtko Ursulin
Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.
If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program
Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.
i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 21
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (8):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: Add DG2_NB_MBD subplatform
drm/i915/dg2: DG2
Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.
Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver
Add DG2 Motherboard Down Config check support.
v2:
- Don't use pciid to check DG2 MBD. [Jani]
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11
Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
From: Priyanka Dandamudi
Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar
to one of the supported sizes.
Akeem G Abodunrin (1):
drm/i915: Add support for LMEM PCIe resizable bar
Priyanka Dandamudi (1):
drm/i915: Add
From: Akeem G Abodunrin
This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
Currently i915 disables d3cold for i915 pci dev.
This blocks D3 for i915 gfx pci upstream bridge (VSP).
Let's disable d3cold at gfx root port to make sure that
i915 gfx VSP can transition to D3 to save some power.
We don't need to disable/enable d3cold in rpm, s2idle
suspend/resume handlers.
From: Diego Santa Cruz
The quirk added in upstream commit 90c3e2198777 ("drm/i915/glk: Add
Quirk for GLK NUC HDMI port issues.") is also required on the ECS Liva
Q2.
Note: Would be nicer to figure out the extra delay required for the
retimer without quirks, however don't know how to check for
== Series Details ==
Series: Do not enable PSR2 if no active planes (rev3)
URL : https://patchwork.freedesktop.org/series/105109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105109v3
Summary
---
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
>
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105220v1
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : warning
== Summary ==
Error: dim checkpatch failed
ab29d65b77e1 drm/i915/wm: move wm state verification to
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
From: Tvrtko Ursulin
We need some coverage of the virtual engines.
Signed-off-by: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
---
tests/i915/drm_fdinfo.c | 284 +++-
1 file changed, 282 insertions(+), 2 deletions(-)
diff --git a/tests/i915/drm_fdinfo.c
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104128v3
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/dgfx: Disable d3cold Correctly (rev2)
URL : https://patchwork.freedesktop.org/series/104770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104770v2
Summary
---
Hi Lakshmi,
Here would be another false positive, I don't see how my changes would
affect debugfs_test@read_all_entries test on kbl.
/Juha-Pekka
to 16. kesäk. 2022 klo 19.31 Patchwork
kirjoitti:
> *Patch Details*
> *Series:* series starting with [1/3] drm/i915/display: Add smem fallback
>
By moving wm state verification to intel_pm.c, we can make a bunch of
functions static, hiding the wm details better. Also declutter
intel_display.c.
v2: intel_wm_state_verify -> intel_wm_verify_state (Ville)
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
v2 of [1]. Address review comments, drop crtc state compare move, add hw
state readout split, and sprinkle some struct
drm_i915_private *i915 cleanups on top.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/105156/
Jani Nikula (11):
drm/i915/wm: move wm state verification to
On Thu, 16 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The WARN shouldn't have been added yet. For the moment the
> clock that gets passed here is just what the user has requested
> (via the modeline) and may not be exactly what iCLKIP can
> generate.
>
> Later on the plan is to
On Wed, 15 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Abstract the bit extraction from the VBT per-panel bitfields
> slightly.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 31 +--
>
== Series Details ==
Series: drm/i915/dsi: add payload receiving code (rev3)
URL : https://patchwork.freedesktop.org/series/105096/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11763_full -> Patchwork_105096v3_full
From: Ville Syrjälä
The WARN shouldn't have been added yet. For the moment the
clock that gets passed here is just what the user has requested
(via the modeline) and may not be exactly what iCLKIP can
generate.
Later on the plan is to change things so that we already get
passed the exact clock
On 15/06/2022 16:20, Niranjana Vishwanathapura wrote:
On Wed, Jun 15, 2022 at 08:22:23AM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:42, Niranjana Vishwanathapura wrote:
On Tue, Jun 14, 2022 at 05:07:37PM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:02, Tvrtko Ursulin wrote:
On
Split out the modeset hardware state readout and sanitize, or state
setup, to a separate file.
Do some drive-by checkpatch fixes while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 730
Prefer struct drm_i915_private *i915 over struct drm_device or dev_priv.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 60 ++--
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
Keep the mpllb implementation details together in intel_snps_phy.c. Also
declutter intel_display.c.
v2: intel_mpllb_verify_state -> void intel_mpllb_state_verify (Ville)
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 46
The pipe_config_mismatch() function is primarily for logging comparison
results.
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git
Add new file intel_modeset_verify.c for high level modeset verification
code to declutter intel_display.h. The new file is supposed to be about
crtc/encoder/connector verification; the state verification for very
specific functionality such as plls or wm should be placed next to the
code it
Declutter intel_display.c by splitting out crtc state dumping to a
separate file.
v2: intel_pipe_config_dump -> intel_crtc_state_dump
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_crtc_state_dump.c | 314 +
Pass struct drm_i915_private * instead of struct drm_device *, and
rename dev_priv to i915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c| 199 +-
.../drm/i915/display/intel_modeset_setup.h
Add the brackets [] around crtc state dump context string in
intel_crtc_state_dump() so the callers don't have to.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
Rename dev_priv to i915 in crtc state dumping code.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_crtc_state_dump.c | 80 +--
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
Keep the shared dpll implementation details together by moving the dpll
state verification to intel_dpll_mgr.c. Also declutter intel_display.c.
v2: intel_shared_dpll_verify_state -> intel_shared_dpll_state_verify (Ville)
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
On Thu, Jun 16, 2022 at 12:48:10PM +0300, Jani Nikula wrote:
> v2 of [1]. Address review comments, drop crtc state compare move, add hw
> state readout split, and sprinkle some struct
> drm_i915_private *i915 cleanups on top.
>
> BR,
> Jani.
>
> [1]
On Fri, 10 Jun 2022, Jouni Högander wrote:
> This patch set disables connector polling when entering runtime
> suspend for headless sku to prevent waking it up again when poll
> is performed.
Pushed to drm-intel-next, thanks for the patches.
BR,
Jani.
>
> v3:
> - dummy
On Wed, 15 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Parsing the panel_type is a bit special and should be done
> before we parse anything else potentially panel-specific from
> the VBT. So move it out from parse_panel_options(). It doesn't
> neet to be there anyway since it'll do
On Wed, 15 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Older VBTs don't have all the stuff we've defined for the
> LVDS options block (40). In particular we're currently parsing
> the DPS panel type bits even though they may not exist, which
> could mean we end up flagging the
On Wed, 15 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the underrun status sanitation into its own helper.
>
> Signed-off-by: Ville Syrjälä
On the series,
Reviewed-by: Jani Nikula
I'll respin my state readout extraction on top of this once you've
merged.
> ---
>
From: Tvrtko Ursulin
Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.
Signed-off-by: Tvrtko Ursulin
Fixes: 055634e4b62f ("drm/i915: Expose client engine utilisation via
From: Tvrtko Ursulin
Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 432 ++
lib/igt_drm_clients.h | 85 +++
lib/meson.build |
From: Tvrtko Ursulin
Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
lib/igt_drm_clients.c | 18 +---
lib/igt_drm_clients.h | 3 ++-
lib/igt_drm_fdinfo.c| 48
From: Tvrtko Ursulin
Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 22 ++
lib/igt_drm_clients.h | 1 +
2 files changed, 15 insertions(+), 8
From: Tvrtko Ursulin
Just a re-send having rebased on top of latest tree.
Tvrtko Ursulin (8):
lib: Extract igt_drm_clients from intel_gpu_top
libdrmfdinfo: Allow specifying custom engine map
libdrmclients: Record client drm minor
libdrmclient: Support multiple DRM cards
libdrmfdinfo:
From: Tvrtko Ursulin
Require DRM minor match during client lookup.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index c23a3fae9793..e11c8b18188f 100644
From: Tvrtko Ursulin
Intel_gpu_top gets it's main engine configuration data via PMU probe and
uses that for per client view as well. Furthemore code so far assumed only
clients belonging from a single DRM card would be tracked in a single
clients list.
Break this inter-dependency by moving the
From: Tvrtko Ursulin
Prep code for incoming work.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 2 ++
lib/igt_drm_fdinfo.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 68c89ad2c17e..b850d2210ae7 100644
---
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from intel_gpu_top but for now omits the fancy
features like interactive functionality, card selection,
From: Tvrtko Ursulin
Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks
On 16/06/2022 15:15, Jani Nikula wrote:
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin
>
> This patch adds support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> From: Tvrtko Ursulin
>
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
>
> Cc: Andi Shyti
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Anshuman Gupta
> ---
>
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
> latency. Enabling
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 15:15, Jani Nikula wrote:
>> On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
>>> On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding
On Thu, 16 Jun 2022, priyanka.dandam...@intel.com wrote:
> From: Akeem G Abodunrin
>
> This patch adds support for the local memory PICe resizable bar, so that
Please use imperative. "Add support ..."
Please don't refer to "this patch".
Please fix your git settings to not prefix with "i-g-t"
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
From: Priyanka Dandamudi
Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar to one of the
supported sizes.
Akeem G Abodunrin (1):
drm/i915: Add support for LMEM PCIe resizable bar
Priyanka Dandamudi (1):
drm/i915: Add
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
== Series Details ==
Series: drm/i915: Remove bogus LPT iCLKIP WARN
URL : https://patchwork.freedesktop.org/series/105221/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11767 -> Patchwork_105221v1
Summary
---
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 13:01, Anshuman Gupta wrote:
>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>> the VRAM Self Refresh feature support. Adding those sub platform
>> accordingly.
>>
>> Cc: Matt Roper
>> Signed-off-by: Anshuman Gupta
>>
On Thu, Jun 16, 2022 at 03:00:56PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Stop displaying engine classes with no engines - it is not a huge problem
if they are shown, since the values will correctly be all zeroes, but it
does count as misleading.
Signed-off-by: Tvrtko Ursulin
On Thu, Jun 16, 2022 at 01:48:16PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Abstract the bit extraction from the VBT per-panel bitfields
> > slightly.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Thu, Jun 16, 2022 at 01:52:38PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Pull the underrun status sanitation into its own helper.
> >
> > Signed-off-by: Ville Syrjälä
>
> On the series,
>
> Reviewed-by: Jani Nikula
Thanks.
>
/drm-tip drm-tip
config: x86_64-defconfig
(https://download.01.org/0day-ci/archive/20220616/202206162239.am4qoo2c-...@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-3) 11.3.0
reproduce (this is a W=1 build):
#
https://github.com/intel-lab-lkp/linux/commit
We have a bug for a similar test timeout on KBL
https://gitlab.freedesktop.org/drm/intel/-/issues/6048
igt@kms_cursor_legacy@pipe-b-torture-move - incomplete - Received signal
SIGQUIT. Per-test timeout exceeded. Killing the current test with SIGQUIT.
Thanks,
Lakshmi.
-Original Message-
/drm-tip drm-tip
config: i386-randconfig-a004
(https://download.01.org/0day-ci/archive/20220616/202206162323.1npq58gh-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
f0e608de27b3d56846eebf3712ab542979d6)
reproduce (this is a W=1 build):
wget
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/priyanka-dandamudi-intel-com/Add-support-for-LMEM-PCIe-resizable-bar/20220616-201631
base: git://anongit.freedesktop.org/drm/drm-tip
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add smem fallback
allocation for dpt (rev4)
URL : https://patchwork.freedesktop.org/series/104983/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104983v4
On 15/06/2022 19:59, Lucas De Marchi wrote:
On Tue, Jun 14, 2022 at 08:07:04AM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 02:10, Umesh Nerlige Ramappa wrote:
On Sat, Jun 11, 2022 at 10:27:11AM -0700, Alan Previn wrote:
Using igt's gem-create and with additional patches to track object
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add smem fallback
allocation for dpt (rev4)
URL : https://patchwork.freedesktop.org/series/104983/
State : warning
== Summary ==
Error: dim checkpatch failed
4c23115bcf5b drm/i915/display: Add smem fallback allocation
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : warning
== Summary ==
Error: dim checkpatch failed
ee513fcc2693 drm/i915/dgfx: OpRegion VRAM Self Refresh Support
341133e9b9ad drm/i915/dg1: OpRegion PCON DG1 MBD config
== Series Details ==
Series: drm/i915: drm/i915/display: split out verification, hw readout and dump
from intel_display.c
URL : https://patchwork.freedesktop.org/series/105220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105220v1_full
== Series Details ==
Series: Do not enable PSR2 if no active planes (rev3)
URL : https://patchwork.freedesktop.org/series/105109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11767_full -> Patchwork_105109v3_full
Summary
== Series Details ==
Series: drm/i915/glk: ECS Liva Q2 needs GLK HDMI port timing quirk
URL : https://patchwork.freedesktop.org/series/105226/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105226v1
== Series Details ==
Series: drm/i915/fdinfo: Don't show engine classes not present
URL : https://patchwork.freedesktop.org/series/105228/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11768 -> Patchwork_105228v1
Summary
== Series Details ==
Series: DG2 VRAM_SR Support (rev3)
URL : https://patchwork.freedesktop.org/series/104128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104128v3_full
Summary
---
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105231/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11769 -> Patchwork_105231v1
Summary
---
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