[Intel-gfx] [PATCH] drm/i915/chv: Recomputing CHV watermark.

From: Abhay abhay.ku...@intel.com Current WM calculation is causing regression on SR residency. Recomputing WM using new formula as provided by VPG Change-Id: I9dbd6a7b70c84454748dee41738130934230b763 Signed-off-by: Abhay abhay.ku...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 26

[Intel-gfx] [PATCH] drm/i915: Suspend resume timing optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Moving 250ms from T12 timing to suspend path so that resume path will be faster. Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/

[Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. Change-Id: Ied0f10f82776af8e6e8ff561bb4e5c0ce1dad4b3 Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/

[Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 3 +++ drivers/

[Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. Change-Id: Ied0f10f82776af8e6e8ff561bb4e5c0ce1dad4b3 Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- dri

[Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle delay calculation(Ville). Cc: Ville Syrjälä <v

[Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle delay calculation(Ville). v3: Addressing Ville

[Intel-gfx] [PATCH v4] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle delay calculation(Ville). v3: Addressed below co

[Intel-gfx] [PATCH V5] drm/i915: edp resume/On time optimization.

From: Abhay Kumar <abhay.ku...@intel.com> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle delay calculation(Ville). v3: Addressed below co

[Intel-gfx] [PATCH] drm/i915: set minimum CD clock to twice the BCLK.

From: Abhay Kumar <abhay.ku...@intel.com> In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz. This chagne will ensure CD clock to be twice of BCLK. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=1029

[Intel-gfx] [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

h once(Abhay). Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/intel_audio.c | 66 +--- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

to avoid any transaction on iDisp link during cdclk change(Abhay). Signed-off-by: Ville Syrjälä Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_audio.c | 87

[Intel-gfx] [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

to avoid any transaction on iDisp link during cdclk change(Abhay). v4: Remove Power well 2 reset workaround(Ville). Signed-off-by: Ville Syrjälä Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK

Patches needed to change cdclk to 2*BCLK before accessing HDA Codec. Ville Syrjälä (2): drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled drm/i915: Shut off PW2 when changing cdclk on glk drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk

Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915/intel_cdclk.c | 14 ++ drivers/gpu/drm/i915/intel_drv.h| 5 + drivers/gpu/drm/i915/intel_runtime_pm.c | 34 + 3 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH v4 0/4] Enable Dynamic cdclk and HDA together on GLK

Patches needed to change cdclk to 2*BCLK before accessing HDA Codec. Ville Syrjälä (4): drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled drm/i915: Introduce for_each_intel_dp() drm/i915: Lock gmbus/aux mutexes while changing cdclk drm/i915: Shut off PW2 when changing

[Intel-gfx] [PATCH v4 2/4] drm/i915: Introduce for_each_intel_dp()

From: Ville Syrjälä Add a convenience macro for iterating DP encoders. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.h | 4 drivers/gpu/drm/i915/intel_dp.c | 38 +++- drivers/gpu/drm/i915/intel_drv.h | 14 + 3

[Intel-gfx] [PATCH v4 4/4] drm/i915: Shut off PW2 when changing cdclk on glk

From: Ville Syrjälä Apparently the audio hardware gets confused if it's powered up when change the cdclk frequency. Force PW2 (which is where audio lives) off when we do the cdclk reprogramming. This is a rather big hack. If something is using PW2 when we do this things wil break. I don't think

[Intel-gfx] [PATCH v4 1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

to avoid any transaction on iDisp link during cdclk change(Abhay). v4: Remove Power well 2 reset workaround(Ville). Signed-off-by: Ville Syrjälä Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 3/4] drm/i915: Lock gmbus/aux mutexes while changing cdclk

From: Ville Syrjälä gmbus/aux may be clocked by cdclk, thus we should make sure no transfers are ongoing while the cdclk frequency is being changed. We do that by simply grabbing all the gmbus/aux mutexes. No one else should be holding any more than one of those at a time so the lock ordering

[Intel-gfx] [PATCH v5] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

to avoid any transaction on iDisp link during cdclk change(Abhay). v4: Remove Power well 2 reset workaround(Ville). v5: Remove unwanted Power well 2 register defined in v4(Abhay). Signed-off-by: Ville Syrjälä Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers

[Intel-gfx] [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

CDCLK has to be at least twice the BLCK regardless of audio. Audio driver has to probe using this hook and increase the clock even in absence of any display. Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/

[Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if possible

From: Ville Syrjälä If we have only a single active pipe and the cdclk change only requires the cd2x divider to be updated bxt+ can do the update with forcing a full modeset on the pipe. Try to hook that up. Signed-off-by: Ville Syrjälä Signed-off-by: Abhay Kumar --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

?id=102937 Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/gpu/drm/i915/intel_audio.c | 33 ++--- drivers/gpu/drm/i915/intel_cdclk.c | 21 + drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 44 insertions(+), 11 deletions

[Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

In glk when device boots with 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz. This chagne will ensure CD clock to be twice of BCLK. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937 Signed-off-by: Abhay Kumar <abhay.ku...@int

[Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

tps://bugs.freedesktop.org/show_bug.cgi?id=102937 Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index dc7