Re: [Intel-gfx] [PATCH v7] drm/i915: Add soft-pinning API for execbuffer

Message- From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] Sent: Wednesday, December 9, 2015 5:36 AM To: Thierry, Michel; Chris Wilson; Daniel, Thomas; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay; Goel, Akash; Kristian Høgsberg Subject: Re: [Intel-gfx] [PATCH v7] drm/i915: Add

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_softpin: Fix compiler warning on 32bit systems

On Thu, Dec 10, 2015 at 04:43:29PM +, Tvrtko Ursulin wrote: > > Hi, > > On 10/12/15 14:58, Mika Kuoppala wrote: > >We get build error as we try to cast from ptr to integer > >of different size on 32 bit platforms. Use unsigned long > >as the cast, it will work with both 32 and 64 bit >

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_softpin: Use offset addresses in canonical form

-Original Message- From: Thierry, Michel Sent: Tuesday, January 5, 2016 10:02 AM To: Belgaumkar, Vinay Subject: RE: [Intel-gfx] [PATCH i-g-t] tests/gem_softpin: Use offset addresses in canonical form > -Original Message- > From: Intel-gfx [mailto:intel-gf

Re: [Intel-gfx] [PATCH v2 i-g-t] tests/gem_softpin: Use offset addresses in canonical form

On Wed, Jan 06, 2016 at 03:00:39PM +, Michel Thierry wrote: > i915 validates that requested offset is in canonical form, so tests need > to convert the offsets as required. > > Also add test to verify non-canonical 48-bit address will be rejected. > > v2: Use sign_extend64 for converting to

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm_test: New tests for buffered SVM feature

AM To: Belgaumkar, Vinay Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm_test: New tests for buffered SVM feature On Tue, Nov 10, 2015 at 07:37:54AM -0800, Vinay Belgaumkar wrote: > v1: These tests exercise the userptr ioctl to create shared buff

Re: [Intel-gfx] [PATCH igt] igt/gem_softpin: Remove false dependencies on esoteric features

[mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Tuesday, January 26, 2016 2:06 AM To: Barnes, Jesse Cc: Daniel Vetter; Belgaumkar, Vinay; Chris Wilson; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH igt] igt/gem_softpin: Remove false dependencies on esoteric features

Re: [Intel-gfx] [PATCH igt] igt/gem_softpin: Remove false dependencies on esoteric features

Hi Chris, These tests were developed for testing buffered SVM(using userptr and soft pinning API). I think Dan wanted me to rename the tests to gem_softpin, since they were being checked in as tests which validated the softpin kernel patches. Can we rename the existing tests to

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm: Buffered SVM tests

-Original Message- From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] Sent: Wednesday, February 24, 2016 5:18 AM To: Belgaumkar, Vinay <vinay.belgaum...@intel.com>; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/gem_buffered_svm: Buffer

Re: [Intel-gfx] [PATCH i-g-t] Add support for subtest-specific documentation

Bump. On 7/11/2017 3:08 PM, Belgaumkar, Vinay wrote: On 6/22/2017 4:30 AM, Petri Latvala wrote: The current documentation for tests is limited to a single string per test binary. This patch adds support for documenting individual subtests. The syntax for subtest documentation

Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests

On 8/9/2017 7:32 AM, Arkadiusz Hiler wrote: On Tue, Aug 08, 2017 at 03:09:00PM -0700, Vinay Belgaumkar wrote: This is an RFC for adding documentation to IGT subtests. Each subtest can have something similar to a WHAT - explaining what the subtest actually does, and a WHY - which explains a

Re: [Intel-gfx] [PATCH i-g-t 1/5] Add support for subtest-specific documentation

On 8/10/2017 3:26 AM, Petri Latvala wrote: The current documentation for tests is limited to a single string per test binary. This patch adds support for documenting individual subtests. The syntax for subtest documentation is: igt_document_subtest("Frob knobs to see if one of the "

Re: [Intel-gfx] [PATCH i-g-t 4/5] testdisplay: Handle subtest documentation flags

On 8/10/2017 3:26 AM, Petri Latvala wrote: testdisplay has no subtests so hook them to existing subtest handling. Signed-off-by: Petri Latvala --- tests/testdisplay.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/testdisplay.c b/tests/testdisplay.c

Re: [Intel-gfx] [PATCH i-g-t 5/5] igt_command_line.sh: Test subtest documentation flag handling

On 8/10/2017 3:26 AM, Petri Latvala wrote: Signed-off-by: Petri Latvala --- tests/igt_command_line.sh | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tests/igt_command_line.sh b/tests/igt_command_line.sh index 7f80fc8..b3a794c

Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests

On 8/10/2017 1:32 AM, Arkadiusz Hiler wrote: On Wed, Aug 09, 2017 at 10:00:16AM -0700, Belgaumkar, Vinay wrote: On 8/9/2017 7:32 AM, Arkadiusz Hiler wrote: On Tue, Aug 08, 2017 at 03:09:00PM -0700, Vinay Belgaumkar wrote: This is an RFC for adding documentation to IGT subtests. Each

Re: [Intel-gfx] [PATCH i-g-t] Add support for subtest-specific documentation

On 6/22/2017 4:30 AM, Petri Latvala wrote: The current documentation for tests is limited to a single string per test binary. This patch adds support for documenting individual subtests. The syntax for subtest documentation is: igt_subtest_documentation("Frob knobs to see if one of the "

Re: [Intel-gfx] [PATCH i-g-t 1/2] Add support for subtest-specific documentation

On 8/9/2017 4:40 AM, Petri Latvala wrote: The current documentation for tests is limited to a single string per test binary. This patch adds support for documenting individual subtests. The syntax for subtest documentation is: igt_document_subtest("Frob knobs to see if one of the "

Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update

On 9/8/2017 12:19 AM, Katarzyna Dec wrote: On Thu, Sep 07, 2017 at 11:28:38AM -0700, Belgaumkar, Vinay wrote: On 9/7/2017 5:15 AM, Katarzyna Dec wrote: Added comments in tricky places for better feature understanding. Added IGT_TEST_DESCRIPTION and short description for non-obvious

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

On 8/30/2017 4:12 AM, Michał Winiarski wrote: On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote: Added the missing IGT_TEST_DESCRIPTION and some subtest descriptions. Signed-off-by: Vinay Belgaumkar --- tests/gem_flink_basic.c | 36

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_flink_basic: Add documentation for subtests

On 8/30/2017 12:39 PM, Michał Winiarski wrote: On Wed, Aug 30, 2017 at 10:49:20AM -0700, Belgaumkar, Vinay wrote: On 8/30/2017 4:12 AM, Michał Winiarski wrote: On Tue, Aug 29, 2017 at 02:25:19PM -0700, Vinay Belgaumkar wrote: Added the missing IGT_TEST_DESCRIPTION and some subtest

Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_flink_basic: Add documentation for subtests

On 9/4/2017 1:30 AM, Daniel Vetter wrote: On Thu, Aug 31, 2017 at 02:33:23PM -0700, Vinay Belgaumkar wrote: Added the missing IGT_TEST_DESCRIPTION and some subtest descriptions. Trying to establish a method to document subtests, it should describe the feature being tested rather than how. The

Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_flink_basic: Add documentation for subtests

On 9/1/2017 4:55 AM, Arkadiusz Hiler wrote: On Thu, Aug 31, 2017 at 02:33:23PM -0700, Vinay Belgaumkar wrote: Added the missing IGT_TEST_DESCRIPTION and some subtest descriptions. Trying to establish a method to document Hey Vinay, Please add appropriate tag to the subject, as this is

Re: [Intel-gfx] [PATCH i-g-t] pm_rps: [RFC] RPS tests documentation update

On 9/7/2017 5:15 AM, Katarzyna Dec wrote: Added comments in tricky places for better feature understanding. Added IGT_TEST_DESCRIPTION and short description for non-obvious subtests. Changed name of 'magic' checkit() function to something meaningfull. Changed junk struct and stuff array names.

Re: [Intel-gfx] [PATCH i-g-t v3] lib/igt_gt: Allow non-default contexts to hang non-render rings

On 10/11/2017 4:23 PM, Daniele Ceraolo Spurio wrote: On 11/10/17 14:31, Vinay Belgaumkar wrote: This limitation does not exist in latest kernel. It was removed by this patch- commit f7978a0c581a8a840a28306f8da43e06e7fef3bf v2: Added commit id that removes the limitation(Chris Wilson) V3:

Re: [Intel-gfx] [PATCH 08/27] drm/i915/icl: Ringbuffer interrupt handling

On 1/15/2018 2:38 AM, Tvrtko Ursulin wrote: On 11/01/2018 19:17, Daniele Ceraolo Spurio wrote: On 10/01/18 02:12, Chris Wilson wrote: Quoting Paulo Zanoni (2018-01-09 23:23:17) From: Tvrtko Ursulin Since it is not possible to mask individual engine instances

Re: [Intel-gfx] [PATCH 08/27] drm/i915/icl: Ringbuffer interrupt handling

On 2/1/2018 3:58 PM, Belgaumkar, Vinay wrote: On 1/15/2018 2:38 AM, Tvrtko Ursulin wrote: On 11/01/2018 19:17, Daniele Ceraolo Spurio wrote: On 10/01/18 02:12, Chris Wilson wrote: Quoting Paulo Zanoni (2018-01-09 23:23:17) From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Limit smoketest to the desired engines

On 2/10/2018 1:00 AM, Chris Wilson wrote: We run the per-engine scheduling smoketests across all engines, the opposite of what was intended! Signed-off-by: Chris Wilson --- tests/gem_exec_schedule.c | 12 1 file changed, 8 insertions(+), 4

Re: [Intel-gfx] [PATCH v4 1/5] i915.rst: Narration overview on GEM + minor reorder to improve narration

On 4/3/2018 3:52 AM, kevin.rogo...@intel.com wrote: From: Kevin Rogovin Add a narration to i915.rst about Intel GEN GPU's: engines, driver context and relocation. Signed-off-by: Kevin Rogovin --- Documentation/gpu/i915.rst | 116

Re: [Intel-gfx] [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc

On 7/10/2021 7:27 AM, Michal Wajdeczko wrote: Hi Vinay, On 10.07.2021 03:20, Vinay Belgaumkar wrote: Add macros to check for slpc support. This feature is currently supported for gen12+ and enabled whenever guc submission is enabled/selected. please try to use consistent names across all

Re: [Intel-gfx] [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc

On 7/10/2021 7:27 AM, Michal Wajdeczko wrote: Hi Vinay, On 10.07.2021 03:20, Vinay Belgaumkar wrote: Add macros to check for slpc support. This feature is currently supported for gen12+ and enabled whenever guc submission is enabled/selected. please try to use consistent names across all

Re: [Intel-gfx] [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini

On 7/10/2021 7:35 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Declare header and source files for SLPC, along with init and enable/disable function templates. later you claim that "disable" is not needed Changed. Signed-off-by: Vinay Belgaumkar

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: remove unneeded clflush calls

On 9/14/2021 12:51 PM, Lucas De Marchi wrote: The clflush calls here aren't doing anything since we are not writting something and flushing the cache lines to be visible to GuC. Here the intention seems to be to make sure whatever GuC has written is visible to the CPU before we read them.

Re: [Intel-gfx] [PATCH 07/16] drm/i915/guc/slpc: Enable slpc and add related H2G events

On 7/10/2021 10:37 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Add methods for interacting with guc for enabling SLPC. Enable SLPC after guc submission has been established. GuC load will s/guc/GuC fail if SLPC cannot be successfully initialized. Add

Re: [Intel-gfx] [PATCH 05/16] drm/i915/guc/slpc: Adding slpc communication interfaces

On 7/10/2021 8:52 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Replicate the SLPC header file in GuC for the most part. There are what you mean by "replicate" here? some SLPC mode based parameters which haven't been included since we are not using them.

Re: [Intel-gfx] [PATCH 06/16] drm/i915/guc/slpc: Allocate, initialize and release slpc

On 7/10/2021 9:05 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Allocate data structures for SLPC and functions for initializing on host side. Signed-off-by: Vinay Belgaumkar Signed-off-by: Sundaresan Sujaritha --- drivers/gpu/drm/i915/gt/uc/intel_guc.c

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

On 7/29/2021 9:21 AM, Michal Wajdeczko wrote: On 28.07.2021 23:11, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest

On 7/29/2021 4:40 PM, Matthew Brost wrote: On Wed, Jul 28, 2021 at 02:11:43PM -0700, Vinay Belgaumkar wrote: Tests that exercise the SLPC get/set frequency interfaces. Clamp_max will set max frequency to multiple levels and check that SLPC requests frequency lower than or equal to it.

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Compare average group occupancy for RPS evaluation

On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote: From: Chris Wilson Currently, we inspect each engine individually and measure the occupancy of that engine over the last evaluation interval. If that exceeds our busyness thresholds, we decide to increase the GPU frequency. However, under a

Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Improve "race-to-idle" at low frequencies

On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote: From: Chris Wilson While the power consumption is proportional to the frequency, there is also a static draw for active gates. The longer we are able to powergate (rc6), the lower the static draw. Thus there is a sweetspot in the

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc/slpc: Add waitboost functionality for SLPC

On 11/1/2021 1:28 PM, Dixit, Ashutosh wrote: On Sun, 31 Oct 2021 21:39:36 -0700, Belgaumkar, Vinay wrote: @@ -945,6 +960,17 @@ void intel_rps_boost(struct i915_request *rq) if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, >fence.flags)) { struct intel_rps *rps = _ONCE

Re: [Intel-gfx] [PATCH v2 0/3] drm/i915/guc/slpc: Implement waitboost for SLPC

On 11/1/2021 1:24 PM, Dixit, Ashutosh wrote: On Sun, 31 Oct 2021 21:39:34 -0700, Belgaumkar, Vinay wrote: Waitboost is a legacy feature implemented in the Host Turbo algorithm. This patch set implements it for the SLPC path. A "boost" happens when user calls gem_wait ioctl on a

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc/slpc: Define and initialize boost frequency

On 11/1/2021 1:26 PM, Dixit, Ashutosh wrote: On Sun, 31 Oct 2021 21:39:35 -0700, Belgaumkar, Vinay wrote: Define helpers and struct members required to record boost info. Boost frequency is initialized to RP0 at SLPC init. Also define num_waiters which can track the pending boost requests

Re: [Intel-gfx] [PATCH 09/16] drm/i915/guc/slpc: Add get max/min freq hooks

On 7/10/2021 10:52 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Add helpers to read the min/max frequency being used by SLPC. This is done by send a h2g command which forces s/h2g/H2G done. SLPC to update the shared data struct which can then be read.

Re: [Intel-gfx] [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature

On 7/10/2021 11:41 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: This feature hands over the control of HW RC6 to the GUC. GUC decides when to put HW into RC6 based on it's internal busyness algorithms. GUCRC needs GUC submission to be enabled, and only supported

Re: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

On 7/10/2021 11:15 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 10/16] drm/i915/guc/slpc: Add debugfs for slpc info

On 7/10/2021 11:08 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: This prints out relevant SLPC info from the SLPC shared structure. We will send a h2g message which forces SLPC to update the shared data structure with latest information before reading it.

Re: [Intel-gfx] [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc

On 7/10/2021 11:20 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Update the get/set min/max freq hooks to work for slpc case as well. Consolidate helpers for requested/min/max frequency get/set to intel_rps where the proper action can be taken depending on

Re: [Intel-gfx] [PATCH 15/16] drm/i915/guc/slpc: slpc selftest

On 7/10/2021 11:29 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Tests that exercise the slpc get/set frequency interfaces. Clamp_max will set max frequency to multiple levels and check that slpc requests frequency lower than or equal to it. Clamp_min will set

Re: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

On 7/10/2021 11:15 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC

On 7/21/2021 10:24 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Add macros to check for SLPC support. This feature is currently supported for Gen12+ and enabled whenever GuC submission is enabled/selected. Include templates for SLPC init/fini and enable. v2:

Re: [Intel-gfx] [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency

On 7/10/2021 10:47 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Add param set h2g helpers to set the min and max frequencies for use by SLPC. Signed-off-by: Sundaresan Sujaritha Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

Re: [Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC

On 7/21/2021 10:26 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Allocate data structures for SLPC and functions for initializing on host side. v2: Address review comments (Michal W) Signed-off-by: Vinay Belgaumkar Signed-off-by: Sundaresan Sujaritha ---

Re: [Intel-gfx] [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events

On 7/21/2021 10:38 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Add methods for interacting with GuC for enabling SLPC. Enable SLPC after GuC submission has been established. GuC load will fail if SLPC cannot be successfully initialized. Add various helper

Re: [Intel-gfx] [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info

On 7/21/2021 11:05 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: This prints out relevant SLPC info from the SLPC shared structure. We will send a h2g message which forces SLPC to update the shared data structure with latest information before reading it. v2:

Re: [Intel-gfx] [PATCH 04/14] drm/i915/guc/slpc: Adding SLPC communication interfaces

On 7/21/2021 10:25 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Add constants and params that are needed to configure SLPC. v2: Add a new abi header for SLPC. Replace bitfields with genmasks. Address other comments from Michal W. Signed-off-by: Vinay Belgaumkar

Re: [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency

On 7/21/2021 10:42 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Add param set h2g helpers to set the min and max frequencies for use by SLPC. v2: Address review comments (Michal W) Signed-off-by: Sundaresan Sujaritha Signed-off-by: Vinay Belgaumkar ---

Re: [Intel-gfx] [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks

On 7/21/2021 11:00 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Add helpers to read the min/max frequency being used by SLPC. This is done by send a H2G command which forces SLPC to update the shared data struct which can then be read. add note that functions

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

On 7/21/2021 11:09 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 14/14] drm/i915/guc/rc: Setup and enable GUCRC feature

On 7/21/2021 11:21 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: This feature hands over the control of HW RC6 to the GuC. GuC decides when to put HW into RC6 based on it's internal busyness algorithms. GUCRC needs GuC submission to be enabled, and only supported

Re: [Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC

On 7/21/2021 11:13 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Update the get/set min/max freq hooks to work for SLPC case as well. Consolidate helpers for requested/min/max frequency get/set to intel_rps where the proper action can be taken depending on

Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events

On 7/27/2021 1:19 PM, Michal Wajdeczko wrote: On 27.07.2021 22:00, Belgaumkar, Vinay wrote: On 7/27/2021 8:12 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add methods for interacting with GuC for enabling SLPC. Enable SLPC after GuC submission has been

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc/slpc: Add SLPC selftest

On 7/27/2021 12:16 PM, Matthew Brost wrote: On Mon, Jul 26, 2021 at 12:07:59PM -0700, Vinay Belgaumkar wrote: Tests that exercise the SLPC get/set frequency interfaces. Clamp_max will set max frequency to multiple levels and check that SLPC requests frequency lower than or equal to it.

Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency

On 7/27/2021 8:24 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add param set h2g helpers to set the min and max frequencies s/h2g/H2G for use by SLPC. v2: Address review comments (Michal W) v3: Check for positive error code (Michal W) Signed-off-by:

Re: [Intel-gfx] [PATCH 09/15] drm/i915/guc/slpc: Add get max/min freq hooks

On 7/27/2021 8:32 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add helpers to read the min/max frequency being used by SLPC. This is done by send a H2G command which forces SLPC to update the shared data struct which can then be read. These helpers will be used

Re: [Intel-gfx] [PATCH 10/15] drm/i915/guc/slpc: Add debugfs for SLPC info

On 7/27/2021 8:37 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: This prints out relevant SLPC info from the SLPC shared structure. We will send a h2g message which forces SLPC to update the s/h2g/H2G ok. shared data structure with latest information

Re: [Intel-gfx] [PATCH 11/15] drm/i915/guc/slpc: Enable ARAT timer interrupt

On 7/27/2021 8:40 AM, Matthew Brost wrote: On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote: This interrupt is enabled during RPS initialization, and now needs to be done by SLPC code. It allows ARAT timer expiry interrupts to get forwarded to GuC. Signed-off-by: Vinay

Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled

On 7/27/2021 3:44 PM, Matthew Brost wrote: On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote: Also ensure uc_init is called before we initialize RPS so that we can check for SLPC support. We do not need to enable up/down interrupts when SLPC is enabled. However, we still need

Re: [Intel-gfx] [PATCH 07/15] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable

On 7/27/2021 5:20 PM, Matthew Brost wrote: On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote: The assumption when it was added was there would be no wakerefs held. However, if we fail to enable SLPC, we will still be holding a wakeref. So this is if intel_guc_slpc_enable()

Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc/slpc: Cache platform frequency limits

On 7/27/2021 9:00 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc/rc: Setup and enable GUCRC feature

On 7/27/2021 8:37 AM, Matt Roper wrote: On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote: This feature hands over the control of HW RC6 to the GuC. GuC decides when to put HW into RC6 based on it's internal busyness algorithms. GUCRC needs GuC submission to be enabled, and

Re: [Intel-gfx] [PATCH 04/15] drm/i915/guc/slpc: Adding SLPC communication interfaces

On 7/27/2021 6:59 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add constants and params that are needed to configure SLPC. v2: Add a new abi header for SLPC. Replace bitfields with genmasks. Address other comments from Michal W. v3: Add slpc H2G format in abi,

Re: [Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events

On 7/27/2021 8:12 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add methods for interacting with GuC for enabling SLPC. Enable SLPC after GuC submission has been established. GuC load will fail if SLPC cannot be successfully initialized. Add various helper

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc/slpc: Initial definitions for SLPC

On 7/27/2021 6:43 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add macros to check for SLPC support. This feature is currently supported for Gen12+ and enabled whenever GuC submission is enabled/selected. Include templates for SLPC init/fini and enable. v2:

Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency

On 7/27/2021 8:24 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Add param set h2g helpers to set the min and max frequencies s/h2g/H2G for use by SLPC. v2: Address review comments (Michal W) v3: Check for positive error code (Michal W) Signed-off-by:

Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc/slpc: Sysfs hooks for SLPC

On 7/27/2021 9:59 AM, Michal Wajdeczko wrote: On 26.07.2021 21:07, Vinay Belgaumkar wrote: Update the get/set min/max freq hooks to work for SLPC case as well. Consolidate helpers for requested/min/max frequency get/set to intel_rps where the proper action can be taken depending on whether

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Correct the param count for unset param

On 2/17/2022 1:41 AM, Tvrtko Ursulin wrote: On 16/02/2022 18:15, Vinay Belgaumkar wrote: SLPC unset param H2G only needs one parameter - the id of the param. Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits") How serious is this? Does it need backporting? If so:

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Don't restart WL for every frequency step

On 1/20/2022 11:40 AM, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* drm/i915/selftests: Don't restart WL for every frequency step *URL:* https://patchwork.freedesktop.org/series/99109/ *State:*failure *Details:*

Re: [Intel-gfx] [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms

On 1/20/2022 2:24 PM, Daniele Ceraolo Spurio wrote: Starting from xehpsdv, bit 0 of of the GuC shim control register has been repurposed, while bit 2 is now reserved, so we need to avoid setting those for their old meaning on newer platforms. Cc: Vinay Belgaumkar Cc: Stuart Summers

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use i915_probe_error instead of drm_err

On 4/13/2022 11:41 PM, Anshuman Gupta wrote: On 2022-04-13 at 04:18:52 +0530, Vinay Belgaumkar wrote: This will ensure we don't have false positives when we run error injection tests. Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 42

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

On 10/16/2023 4:24 PM, John Harrison wrote: On 10/16/2023 15:55, Vinay Belgaumkar wrote: This bit does not cause an explicit L3 flush. We already use At all? Or only on newer hardware? And as a genuine spec change or as a bug / workaround? If the hardware has re-purposed the bit then it is

Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Set min/max to expected values

On 9/20/2023 7:07 AM, Rodrigo Vivi wrote: On Mon, Sep 18, 2023 at 12:02:59PM -0700, Vinay Belgaumkar wrote: A prior(rps) test leaves the system in a bad state causing failures in the basic test. Why? What was the freq immediately before the failure that made the machine to be busted and not

Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow users to disable waitboost

On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote: On 20/09/2023 22:56, Vinay Belgaumkar wrote: Provide a bit to disable waitboost while waiting on a gem object. Waitboost results in increased power consumption by requesting RP0 while waiting for the request to complete. Add a bit in the gem_wait()

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Add support for w/a KLVs

On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote: From: John Harrison To prevent running out of bits, new w/a enable flags are being added via a KLV system instead of a 32 bit flags word. Signed-off-by: John Harrison --- .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Enable Wa_16019325821

On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote: From: John Harrison Some platforms require holding RCS context switches until CCS is idle (the reverse w/a of Wa_14014475959). Some platforms require both versions. Signed-off-by: John Harrison ---

Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Enable WA 14018913170

On 9/14/2023 3:28 PM, john.c.harri...@intel.com wrote: From: Daniele Ceraolo Spurio The GuC handles the WA, the KMD just needs to set the flag to enable it on the appropriate platforms. Signed-off-by: John Harrison Signed-off-by: Daniele Ceraolo Spurio ---

Re: [Intel-gfx] [PATCH] drm/i915: Read a shadowed mmio register for ggtt flush

On 11/9/2023 11:30 AM, Ville Syrjälä wrote: On Thu, Nov 09, 2023 at 11:21:48AM -0800, Vinay Belgaumkar wrote: We read RENDER_HEAD as a part of the flush. If GT is in deeper sleep states, this could lead to read errors since we are not using a forcewake. Safer to read a shadowed register

Re: [Intel-gfx] [PATCH] drm/i915: Read a shadowed mmio register for ggtt flush

On 11/9/2023 12:35 PM, Ville Syrjälä wrote: On Thu, Nov 09, 2023 at 12:01:26PM -0800, Belgaumkar, Vinay wrote: On 11/9/2023 11:30 AM, Ville Syrjälä wrote: On Thu, Nov 09, 2023 at 11:21:48AM -0800, Vinay Belgaumkar wrote: We read RENDER_HEAD as a part of the flush. If GT is in deeper sleep

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost

On 5/6/2022 9:43 AM, John Harrison wrote: On 5/6/2022 00:18, Tvrtko Ursulin wrote: On 05/05/2022 19:36, John Harrison wrote: On 5/5/2022 10:21, Belgaumkar, Vinay wrote: On 5/5/2022 5:13 AM, Tvrtko Ursulin wrote: On 05/05/2022 06:40, Vinay Belgaumkar wrote: SLPC min/max frequency updates

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Add a new SLPC selftest

On 6/22/2022 1:32 PM, Dixit, Ashutosh wrote: On Fri, 10 Jun 2022 16:47:12 -0700, Vinay Belgaumkar wrote: This test will validate we can achieve actual frequency of RP0. Pcode grants frequencies based on what GuC is requesting. However, thermal throttling can limit what is being granted. Add a

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Add a new SLPC selftest

On 6/24/2022 8:59 PM, Dixit, Ashutosh wrote: On Thu, 23 Jun 2022 16:33:20 -0700, Vinay Belgaumkar wrote: +static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq) +{ + struct intel_gt *gt = rps_to_gt(rps); + u32 perf_limit_reasons; +

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Add a new SLPC selftest

On 6/24/2022 8:59 PM, Dixit, Ashutosh wrote: On Thu, 23 Jun 2022 16:21:46 -0700, Belgaumkar, Vinay wrote: On 6/22/2022 1:32 PM, Dixit, Ashutosh wrote: On Fri, 10 Jun 2022 16:47:12 -0700, Vinay Belgaumkar wrote: This test will validate we can achieve actual frequency of RP0. Pcode grants

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Add a new SLPC selftest

On 6/24/2022 8:59 PM, Dixit, Ashutosh wrote: On Thu, 23 Jun 2022 16:33:20 -0700, Vinay Belgaumkar wrote: +static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq) +{ + struct intel_gt *gt = rps_to_gt(rps); + u32 perf_limit_reasons; +

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc/slpc: Add a new SLPC selftest (rev4)

From: Patchwork Sent: Monday, June 27, 2022 10:00 PM To: Belgaumkar, Vinay Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/guc/slpc: Add a new SLPC selftest (rev4) Patch Details Series: drm/i915/guc/slpc: Add a new SLPC selftest (rev4) URL: https

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost

On 6/21/2022 5:26 PM, Dixit, Ashutosh wrote: On Sat, 14 May 2022 23:05:06 -0700, Vinay Belgaumkar wrote: SLPC min/max frequency updates require H2G calls. We are seeing timeouts when GuC channel is backed up and it is unable to respond in a timely fashion causing warnings and affecting CI.

Re: [Intel-gfx] [PATCH] drm/i915: Add global forcewake status to drpc

On 6/17/2022 1:53 PM, Dixit, Ashutosh wrote: On Fri, 17 Jun 2022 13:25:34 -0700, Vinay Belgaumkar wrote: We have seen multiple RC6 issues where it is useful to know which global forcewake bits are set. Add this to the 'drpc' debugfs output. A couple of optional nits below to look at but

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost

On 5/6/2022 12:18 AM, Tvrtko Ursulin wrote: On 05/05/2022 19:36, John Harrison wrote: On 5/5/2022 10:21, Belgaumkar, Vinay wrote: On 5/5/2022 5:13 AM, Tvrtko Ursulin wrote: On 05/05/2022 06:40, Vinay Belgaumkar wrote: SLPC min/max frequency updates require H2G calls. We are seeing

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost

On 5/5/2022 5:13 AM, Tvrtko Ursulin wrote: On 05/05/2022 06:40, Vinay Belgaumkar wrote: SLPC min/max frequency updates require H2G calls. We are seeing timeouts when GuC channel is backed up and it is unable to respond in a timely fashion causing warnings and affecting CI. Is it the

Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Support OA when Wa_16011777198 is enabled

On 9/26/2022 11:19 AM, Umesh Nerlige Ramappa wrote: On Mon, Sep 26, 2022 at 08:56:01AM -0700, Dixit, Ashutosh wrote: On Fri, 23 Sep 2022 13:11:53 -0700, Umesh Nerlige Ramappa wrote: From: Vinay Belgaumkar Hi Umesh/Vinay, @@ -3254,6 +3265,24 @@ static int i915_oa_stream_init(struct

Re: [Intel-gfx] [PATCH v3] drm/i915/slpc: Optmize waitboost for SLPC

On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote: On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote: Hi Vinay, Waitboost (when SLPC is enabled) results in a H2G message. This can result in thousands of messages during a stress test and fill up an already full CTB. There is no need to

Re: [Intel-gfx] [PATCH] drm/i915/slpc: Optmize waitboost for SLPC

On 10/19/2022 2:12 PM, Belgaumkar, Vinay wrote: On 10/19/2022 12:40 AM, Tvrtko Ursulin wrote: On 18/10/2022 23:15, Vinay Belgaumkar wrote: Waitboost (when SLPC is enabled) results in a H2G message. This can result in thousands of messages during a stress test and fill up an already full

Re: [Intel-gfx] [PATCH] drm/i915/slpc: Optmize waitboost for SLPC

On 10/19/2022 12:40 AM, Tvrtko Ursulin wrote: On 18/10/2022 23:15, Vinay Belgaumkar wrote: Waitboost (when SLPC is enabled) results in a H2G message. This can result in thousands of messages during a stress test and fill up an already full CTB. There is no need to request for RP0 if GuC is

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