Re: [Intel-gfx] [PATCH] drm/i915/vlv: T12 eDP panel timing enforcement during reboot

On 07/02/2014 01:35 AM, Jani Nikula wrote: From: Clint Taylor clinton.a.tay...@intel.com The panel power sequencer on vlv doesn't appear to accept changes to its T12 power down duration during warm reboots. This change forces a delay for warm reboots to the T12 panel timing as defined

Re: [Intel-gfx] [PATCH] drm/i915/vlv: T12 eDP panel timing enforcement during reboot

On 07/02/2014 07:40 AM, Paulo Zanoni wrote: 2014-07-02 5:35 GMT-03:00 Jani Nikula jani.nik...@intel.com: From: Clint Taylor clinton.a.tay...@intel.com The panel power sequencer on vlv doesn't appear to accept changes to its T12 power down duration during warm reboots. This change forces

Re: [Intel-gfx] [PATCH] drm/i915: remove pixel doubled HDMI modes from valid modes list

On 08/11/2014 11:59 PM, Daniel Vetter wrote: On Tue, Aug 12, 2014 at 07:39:24AM +0100, Chris Wilson wrote: On Mon, Aug 11, 2014 at 03:33:02PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Intel HDMI does not correctly configure pixel replicated HDMI

Re: [Intel-gfx] [PATCH 0/4] drm/i915: backlight sysfs bl_power and brightness == 0

On 08/12/2014 07:11 AM, Jani Nikula wrote: This series adds support for backlight class sysfs bl_power attribute for eDP panels, which allows switching the backlight on/off. This is done using the eDP panel power control as a sub-state of everything else being enabled. Patch 4 also makes 0

Re: [Intel-gfx] [PATCH 1/4] drm/i915/dp: split up panel power control from backlight pwm control

On 08/12/2014 07:11 AM, Jani Nikula wrote: Make it possible to change panel power control backlight state without touching the PWM. No functional changes. Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 39 ++- 1 file

Re: [Intel-gfx] [PATCH] drm: HDMI pixel replication modes now hactive of 720 for pixel replication

On 08/12/2014 04:07 AM, Ville Syrjälä wrote: On Tue, Jul 29, 2014 at 02:58:23PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com CEA SD interlaced modes use a horizontal 720 pixels that are pixel replicated to 1440. The current driver reports 1440 pixel

Re: [Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

On 08/14/2014 11:48 AM, Ville Syrjälä wrote: On Thu, Aug 14, 2014 at 11:09:25AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Pixel replicated modes should be 720 horizontal pixel and pixel replicated by the HW across the HDMI cable at 2X pixel clock

Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: make backlight bl_power control power sequencer backlight

On 08/12/2014 07:11 AM, Jani Nikula wrote: This lets the userspace switch off the backlight using the backlight class sysfs bl_power file. The switch is done using the power sequencer; the backlight PWM, and everything else, remains enabled. The display backlight won't draw power, but for

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

On 08/18/2014 12:15 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check and flatten the rest of the function. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

Re: [Intel-gfx] [PATCH 1/4] drm/i915/dp: split up panel power control from backlight pwm control

On 08/12/2014 07:11 AM, Jani Nikula wrote: Make it possible to change panel power control backlight state without touching the PWM. No functional changes. Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 39 ++- 1 file

Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: make backlight bl_power control power sequencer backlight

On 08/12/2014 07:11 AM, Jani Nikula wrote: This lets the userspace switch off the backlight using the backlight class sysfs bl_power file. The switch is done using the power sequencer; the backlight PWM, and everything else, remains enabled. The display backlight won't draw power, but for

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: add some framework for backlight bl_power support

On 08/13/2014 02:10 AM, Jani Nikula wrote: Make backlight class sysfs bl_power a sub-state of backlight enabled, if a backlight power connector callback is defined. It's up to the connector callback to handle the sub-state, typically in a way that respects panel power sequencing. v2: Post the

Re: [Intel-gfx] [PATCH 4/4] drm/i915: switch off backlight for backlight class 0 brightness

On 08/12/2014 07:11 AM, Jani Nikula wrote: Make backlight class sysfs brightness 0 value switch off the backlight for connectors that have the backlight_power callback defined. For eDP, this has the similar caveats regarding power savings as bl_power as only the power sequencer backlight control

Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

On 08/20/2014 04:23 AM, Ville Syrjälä wrote: On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Backlight on delay uses PWM enable time to seperate PWM to backlight enable assert. Previous time difference used timing from

Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

...@linux.intel.com] Sent: Friday, August 22, 2014 6:07 AM To: Taylor, Clinton A; Ville Syrjälä; Runyan, Arthur J Cc: Intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert +Art On Thu, 21 Aug 2014, Clint Taylor clinton.a.tay

Re: [Intel-gfx] [PATCH] drm/i915: revert intel_dp_probe_oui call during HPD interrupt handler

On 06/06/2014 02:41 AM, Jani Nikula wrote: On Thu, 05 Jun 2014, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Jun 04, 2014 at 03:29:41PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Remove OUI read function from the lower half interrupt handler. Upon

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

that the PANEL_POWER_RESET bit doesn't actually work as advertised in the docs? *shrug* experimental evidence? commit 01527b3127997ef6370d5ad4fa25d96847fbf12a Author: Clint Taylor clinton.a.tay...@intel.com Date: Mon Jul 7 13:01:46 2014 -0700 drm/i915/vlv: T12 eDP panel timing enforcement during

Re: [Intel-gfx] [PATCH i-g-t 1/3] lib: add kmstest_edid_add_3d

On 08/20/2014 03:54 AM, Thomas Wood wrote: kmstest_edid_add_3d adds an EDID extension block with 3D support to a copy of the specified EDID. Signed-off-by: Thomas Wood thomas.w...@intel.com --- lib/igt_kms.c | 80 +++ lib/igt_kms.h | 1

Re: [Intel-gfx] [PATCH] drm/i915: Enable pixel replicated modes on BDW and HSW.

On 09/24/2014 01:51 AM, Daniel Vetter wrote: On Tue, Sep 23, 2014 at 11:06:56AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

On 09/26/2014 09:38 AM, Ville Syrjälä wrote: On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/30/2014 05:46 AM, Ville Syrjälä wrote: On Fri, Sep 26, 2014 at 09:28:50AM -0700, Clint Taylor wrote: On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock

Re: [Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

On 10/07/2014 01:52 AM, Ville Syrjälä wrote: On Mon, Oct 06, 2014 at 03:01:46PM -0700, Clint Taylor wrote: On 09/26/2014 09:28 AM, Ville Syrjälä wrote: On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com HDMI audio clock

Re: [Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

On 09/26/2014 09:28 AM, Ville Syrjälä wrote: On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com HDMI audio clock config was incorrectly choosing the default for pixel doubled interlaced modes. The table was missing pixel

Re: [Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

On 12/03/2014 01:01 PM, Ville Syrjälä wrote: On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Added PIPE C register support for CHV audio programming. nak. The offset between the pipes looks constant so it should work

Re: [Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

On 12/04/2014 12:41 AM, Jani Nikula wrote: On Wed, 03 Dec 2014, Clint Taylor clinton.a.tay...@intel.com wrote: On 12/03/2014 01:01 PM, Ville Syrjälä wrote: On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Added PIPE C

Re: [Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

On 12/04/2014 11:08 AM, Clint Taylor wrote: On 12/04/2014 12:41 AM, Jani Nikula wrote: On Wed, 03 Dec 2014, Clint Taylor clinton.a.tay...@intel.com wrote: On 12/03/2014 01:01 PM, Ville Syrjälä wrote: On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote: From: Clint

Re: [Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

On 12/05/2014 05:23 AM, Imre Deak wrote: On Fri, 2014-12-05 at 13:57 +0200, Jani Nikula wrote: On Fri, 05 Dec 2014, Imre Deak imre.d...@intel.com wrote: On Fri, 2014-12-05 at 10:37 +0200, Jani Nikula wrote: On Fri, 05 Dec 2014, Clint Taylor clinton.a.tay...@intel.com wrote: On 12/04/2014 11

Re: [Intel-gfx] [PATCH 12/17] drm/i915: Update intel_dp_compute_config() to handle compliance test requests

On 12/17/2014 09:04 AM, Paulo Zanoni wrote: 2014-12-10 21:53 GMT-02:00 Todd Previte tprev...@gmail.com: Adds provisions in intel_dp_compute_config() to accommodate compliance testing. Mostly this invovles circumventing the automatic link configuration parameters and allowing the compliance code

Re: [Intel-gfx] [PATCH] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

On 04/09/2015 01:20 PM, Ville Syrjälä wrote: On Thu, Apr 09, 2015 at 10:17:05AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Latest version of the CHV DPIO programming notes no longer requires writes to TX DW 11 to fix a +2UI interpair skew issue

Re: [Intel-gfx] [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite

On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Turns out the VLV/CHV system agent doesn't understand memory latencies, so trying to rely on the PND deadline mechanism is not going to fly especially when DDR DVFS is enabled.

Re: [Intel-gfx] [PATCH 05/10] drm/i915: Compute display FIFO split dynamically for CHV

); + vlv_write_wm_values(intel_crtc, wm); DRM_DEBUG_KMS(Setting FIFO watermarks - %c: plane=%d, cursor=%d, Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel

Re: [Intel-gfx] [PATCH 09/10] drm/i915: Add debugfs knobs for VLVCHV memory latency values

; + else if (IS_VALLEYVIEW(dev)) + num_levels = 1; + else + num_levels = ilk_wm_max_level(dev) + 1; + if (len = sizeof(tmp)) return -EINVAL; Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay

Re: [Intel-gfx] [PATCH 07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable

, true); - } if (wm.level = VLV_WM_LEVEL_PM5 dev_priv-wm.vlv.level VLV_WM_LEVEL_PM5) Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel

Re: [Intel-gfx] [PATCH 06/10] drm/i915: Use the memory latency based WM computation on VLV too

, struct drm_crtc *crtc) I915_WRITE(SPSURF(pipe, plane), 0); POSTING_READ(SPSURF(pipe, plane)); - - intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); } static void Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay

Re: [Intel-gfx] [PATCH 08/10] drm/i915: Don't do PM5/DDR DVFS with multiple pipes

; + for_each_intel_crtc(dev, crtc) { struct vlv_wm_state *wm_state = crtc-wm_state; enum pipe pipe = crtc-pipe; Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing

Re: [Intel-gfx] [PATCH 10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV

-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite

On 06/26/2015 12:48 PM, Ville Syrjälä wrote: On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote: On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Turns out the VLV/CHV system agent doesn't understand memory latencies, so

Re: [Intel-gfx] [PATCH 03/10] drm/i915: Read wm values from hardware at init on CHV

) { struct drm_i915_private *dev_priv = dev-dev_private; Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org

Re: [Intel-gfx] [PATCH 02/10] drm/i915: Split atomic wm update to pre and post variants

; /* Sleepable operations to perform after commit */ Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo

Re: [Intel-gfx] [PATCH 01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr()

); I915_WRITE(INSTPM, val); + POSTING_READ(INSTPM); } else { return; } Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk=czclk

{ Although not part of this review the else clause is setting PFI_CREDIT to 15 when the BPSEC states that the default of 8 should be used when cdclk/czclk 1. According to the original patch, 15 is the optimal value as stated by another driver team. Reviewed-by: Clint Taylor clinton.a.tay

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV

alignment. Reviewed-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015)

*dev) Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: 4K audio N value incorrect at 29.97 and 23.98 refresh rate

On 10/08/2015 05:44 AM, Ville Syrjälä wrote: On Thu, Oct 08, 2015 at 03:39:26PM +0300, Jani Nikula wrote: On Thu, 08 Oct 2015, Ville Syrjälä <ville.syrj...@linux.intel.com> wrote: On Wed, Oct 07, 2015 at 02:38:29PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clin

Re: [Intel-gfx] [PATCH 2/2] drm/i915: initialize backlight max from VBT

On 08/26/2015 12:58 AM, Jani Nikula wrote: Normally we determine the backlight PWM modulation frequency (which we also use as backlight max value) from the backlight registers at module load time, expecting the registers have been initialized by the BIOS. If this is not the case, we fail. The

Re: [Intel-gfx] [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

of the function with no change in functionality. Reviewed-by: Clint Taylor clinton.a.tay...@intel.com Tested-by: Clint Taylor clinton.a.tay...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman

Re: [Intel-gfx] [PATCH 0/2] drm/i915: initialize backlight pwm from vbt if needed

On 08/26/2015 12:58 AM, Jani Nikula wrote: This is a rebase of [1] and originally [2]. I haven't tried this in a year and I have no idea if it works on SKL, and it's not implemented for BXT. However there's renewed interest, so here's the rebase. Renewed interest as an ODM has been reporting

Re: [Intel-gfx] [PATCH] drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOS

G_DDR_SETUP2); + if ((val & FORCE_DDR_HIGH_FREQ) == 0) + wm->level = VLV_WM_LEVEL_DDR_DVFS; + } mutex_unlock(_priv->rps.hw_lock); } Nice. Reviewed-by: Clint Taylor <clinton

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: initialize backlight max from VBT

code. Cc: Clint Taylor <clinton.a.tay...@intel.com> Signed-off-by: Jani Nikula <jani.nik...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h| 2 + drivers/gpu/drm/i915/i915_reg.h| 3 + drivers/gpu/drm/i915/intel_panel.c | 187 +++-- 3 files

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: don't hard code vlv backlight frequency if unset

On 09/04/2015 06:55 AM, Jani Nikula wrote: Fall back to VBT based backlight modulation frequency if it's not set. Do not hard code. This could be a problem if there is no VBT. Cc: Clint Taylor <clinton.a.tay...@intel.com> Signed-off-by: Jani Nikula <jani.nik...@intel.com> --- dri

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: use pch backlight override on hsw too

the CPU for clarity. Cc: Clint Taylor <clinton.a.tay...@intel.com> Signed-off-by: Jani Nikula <jani.nik...@intel.com> --- drivers/gpu/drm/i915/intel_panel.c | 34 +++--- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

Re: [Intel-gfx] [PATCH] drm/i915: eDP HPD connected check to reduce T3 time

On 09/22/2015 10:27 AM, Ville Syrjälä wrote: On Tue, Sep 22, 2015 at 10:09:39AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> To reduce eDP T3 time check for digital port connected instead of msleep. Maintain VBT time if HPD is not as

Re: [Intel-gfx] [PATCH] drm/i915/skl: CDCLK change during modeset based on VCO in use.

On 11/20/2015 05:55 AM, Ville Syrjälä wrote: On Thu, Nov 19, 2015 at 09:20:16AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Add SKL and KBL cdclk changes during modeset. Taking into account new linkrates available using 8640 VCO. Sign

Re: [Intel-gfx] [PATCH] drm/i915: reboot notifier delay for eDP panels

On 01/12/2016 05:21 AM, Ville Syrjälä wrote: On Mon, Jan 11, 2016 at 01:52:17PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Add reboot notifier for all platforms. This guarantees T12 delay compliance during reboot cycles when pre-os e

Re: [Intel-gfx] [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

On 02/12/2016 03:18 AM, Ville Syrjälä wrote: On Thu, Feb 11, 2016 at 03:22:08PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset to set cdclk based on the max required pixel

Re: [Intel-gfx] [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

On 02/25/2016 05:49 AM, Ville Syrjälä wrote: On Tue, Feb 16, 2016 at 09:44:55AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Set cdclk based on the max required pixel clock based on VCO selected. Track boot vco instead of boot cdclk. The vco

Re: [Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

> still trying to understand the flow but is "ctrl1"/"VCO" in this patch written to DPLL_CTRL1 before we change the CD Clock ? if not then it might be a bug and must be fixed as part of changes here. regards, Sivakumar On 2/10/2016 5:58 AM, clinton.a.t

Re: [Intel-gfx] [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

On 03/16/2016 12:27 AM, Daniel Vetter wrote: On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during

Re: [Intel-gfx] [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

On 03/10/2016 12:08 AM, Maarten Lankhorst wrote: Op 09-03-16 om 22:58 schreef clinton.a.tay...@intel.com: From: Clint Taylor <clinton.a.tay...@intel.com> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occur

Re: [Intel-gfx] [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

On 03/17/2016 02:18 PM, Rodrigo Vivi wrote: On Wed, Mar 16, 2016 at 4:33 PM Clint Taylor <clinton.a.tay...@intel.com <mailto:clinton.a.tay...@intel.com>> wrote: On 03/16/2016 12:27 AM, Daniel Vetter wrote: > On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.t

Re: [Intel-gfx] [PATCH] intel: Adding missing Broxton PCI IDs.

(IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ Device list now matches the kernels entries. Thanks. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lis

Re: [Intel-gfx] [PATCH] drm/i915: Shut down displays gracefully on reboot

imeout requirement is being meet at >500ms during reboot and suspend/resume. Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h |

Re: [Intel-gfx] [PATCH] drm/i915: prevent crash with .disable_display parameter

On 01/18/2017 01:52 AM, Chris Wilson wrote: On Tue, Jan 17, 2017 at 04:37:28PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The .disable_display parameter was causing a fatal crash when fbdev was dereferenced during driver init. The other

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/23/2017 10:23 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: On 03/23/2017 05:30 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Several major vendor

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/24/2017 04:25 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: I would prefer a solution for B (rules for M/N), but the code doesn't appear to be broken and I don't believe we should "Fix" something that is working. The d

Re: [Intel-gfx] [PATCH] drm/i915/dp: reduce link M/N parameters

a: https://bugs.freedesktop.org/show_bug.cgi?id=93578 Tested-by: Mads <m...@ab3.no> Tested-by: PJ <foo...@pjmodos.net> Tested-by: François Guerraz <kubr...@fgv6.net> Tested-by: Lev Popov <l...@nabam.net> Tested-by: Igor Krivenko <igor.s.krive...@gmail.com> Cc: Clint Taylor &

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/23/2017 05:30 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane signal if the Data Link N is greater than 0x8. Patch detec

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

stedt, Marta <marta.lofst...@intel.com> Subject: [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read. Adjust the t

Re: [Intel-gfx] [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read

com>; Lofstedt, Marta <marta.lofst...@intel.com> Subject: [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID re

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

On 08/14/2017 07:40 AM, Daniel Vetter wrote: On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read.

Re: [Intel-gfx] [PATCH i-g-t] tools/intel_vbt_decode: Fix decoding of child device structure

This patch fixes the alignment. I spotted another issue with teh structure and will fix it once this one is merged. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> Tested-by: Clint Taylor <clinton.a.tay...@intel.com> On 08/16/2017 07:20 AM, ville.syrj...@linux.intel.com

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 07/11/2017 07:10 AM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 07/09/2017 11:53 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Cannonlake color init.

Reviewed-by: Clinton Taylor <clinton.a.tay...@intel.com> -Clint On 07/06/2017 02:01 PM, Rodrigo Vivi wrote: Cannonlake has same color setup as Geminilake. Legacy color load luts doesn't work anymore on Cannonlake+. Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Ander Conselvan

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Set scaler mode for NV12

Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor -Clint On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode,

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.

for this information. Cc: Clint Taylor <clinton.a.tay...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_bios.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Update format_is_yuv() to include NV12

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to format_is_yuv() function and made it available for both primary and sprite planes small nit on the commit message: static function in intel_sprite.c is not available

Re: [Intel-gfx] [PATCH] drm/i915/cnl: New DMC release: 1.05.

On 07/12/2017 04:47 PM, Rodrigo Vivi wrote: Version 1.05 is now available for CNL. According to its release notes the only difference is: - Change from aux A pwrreq always turn on during restore, to saving and restoring aux A pwrreq. Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 17 - 1 file changed, 16

Re: [Intel-gfx] [PATCH i-g-t] lib/cfl: Introduce Coffeelake platform definition.

Identical to other platforms. Reviewed-by: Clinton Taylor On 06/29/2017 10:18 AM, Rodrigo Vivi wrote: Coffeelake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. On following patches we

Re: [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 12 +++- 1 file changed, 11

Re: [Intel-gfx] [RESEND i-g-t 3/3] lib/cfl: Add PCI Ids for U SKU in CFl

On 06/22/2017 09:28 AM, Anusha Srivatsa wrote: From: anushasr Follow the spec and add ID for U SKU v2: Update IDs in accordance to the kernel commit: d29fe702c9cb682df99146d24d06e5455f043101 (Chris) Cc: Rodrigo Vivi Signed-off-by: Anusha

Re: [Intel-gfx] [PATCH libdrm 2/3] intel: PCI Ids for H SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 8 +++- 1 file changed, 7

Re: [Intel-gfx] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for

Re: [Intel-gfx] [PATCH i-g-t 2/5] lib/cnl: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also

Re: [Intel-gfx] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy

Re: [Intel-gfx] [PATCH i-g-t 3/5] lib/cnl: Add Cannonlake PCI IDs for Y-skus.

Matches i915 support PCI device IDs Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for

Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

Looks Good. Reviewed-by: Clinton Taylor -Clint On 06/28/2017 05:14 PM, Manasi Navare wrote: This patch fixes the DP AUX CH timeouts observed during CI IGT tests thus fixing the CI failures. This is done by adding a quirk for a particular PCI device that requires

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Add NV12 as supported format for primary plane

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to intel_framebuffer_init

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Upscale scaler max scale for NV12

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) Needs rebase again. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read

Of clinton.a.tay...@intel.com Sent: Friday, August 4, 2017 9:23 PM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very

Re: [Intel-gfx] [PATCH] drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts

On 08/16/2017 02:19 PM, Rodrigo Vivi wrote: It seems this quirk is randomly masking the real issue. It could be masking the real issue. The most likely cause of this issue is a slow power fall off to the panel when the PPS requests power-off. We would need physical access to the platform

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 02:57 AM, Jani Nikula wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The Analogix 7737 DP to HDMI converter requires reduced M and N values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9 via the DPCD quirk list. v2 by Jani: R

Re: [Intel-gfx] [PATCH 1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

properly. Naturally, the workaround of reducing main link attributes for all devices ended up in regressions for other devices. So here we are. Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay..

Re: [Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 03:03 AM, Jani Nikula wrote: On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The Analogix 7737 DP to HDMI converter requires reduced N and M values when to operate correctly at HBR2. Detect this IC by its OUI

Re: [Intel-gfx] [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

devices ended up in regressions for other devices. So here we are. v2: Rebase on DRM DP desc read helpers Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Adam Jackson &l

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