Re: [Intel-gfx] [PATCH 7/7] drm/i915/vlv: Use Blitter Engine to clear out contents of Stolen frame buffers

Sorry we have never received the i915_gem_exec.c file . Please share that, we don't see it in the drm-intel-next also. Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, January 09, 2014 3:16 PM To: Goel, Akash Cc: intel-gfx

Re: [Intel-gfx] [PATCH 5/7] drm/i915/vlv: Increase the utilization of stolen memory on VLV.

platforms, like from CHV onwards. For low RAM based products on BYT, it became imperative for us to fully utilize the Stolen space. Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, January 09, 2014 3:18 PM To: Goel, Akash Cc

Re: [Intel-gfx] [PATCH 5/7] drm/i915/vlv: Increase the utilization of stolen memory on VLV.

Of Daniel Vetter Sent: Thursday, January 09, 2014 12:57 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 5/7] drm/i915/vlv: Increase the utilization of stolen memory on VLV. On Thu, Jan 09, 2014 at 11:01:02AM +0530, akash.g...@intel.com wrote: From: Akash Goel

Re: [Intel-gfx] [PATCH 3/7] drm/i915/vlv: Not reallocating VLV PCTX upon every suspend/resume

To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915/vlv: Not reallocating VLV PCTX upon every suspend/resume On Thu, Jan 09, 2014 at 11:00:42AM +0530, akash.g...@intel.com wrote: From: Akash Goel akash.g...@intel.com VLV PCTX will come from stolen

Re: [Intel-gfx] [PATCH 5/7] drm/i915/vlv: Increase the utilization of stolen memory on VLV.

-Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Friday, January 10, 2014 2:57 PM To: Goel, Akash Cc: Daniel Vetter; Vetter, Daniel; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 5/7] drm/i915/vlv: Increase the utilization

Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV.

Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, January 09, 2014 5:02 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV. On Thu

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added/removed Render specific Hw Workarounds for VLV

these workarounds are applicable to VLV only will not affect any other platforms. So probably it can be pushed as it is without splitting. Best Regards Akash -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Thursday, January 09, 2014 5:56 PM To: Goel, Akash; intel

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added/removed Render specific Hw Workarounds for VLV

workarounds are fragile by definition, and should be separate patches. Understood your concern, will split the work in multiple patches. Best Regards Akash -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Monday, January 20, 2014 1:50 PM To: Goel, Akash; intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support

Please kindly review this patch. Best regards Akash -Original Message- From: Goel, Akash Sent: Thursday, January 09, 2014 5:55 PM To: intel-gfx@lists.freedesktop.org Cc: Goel, Akash Subject: [PATCH] drm/i915/vlv: Added write-enable pte bit support From: Akash Goel akash.g...@intel.com

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support

- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Thursday, February 06, 2014 11:06 PM To: Chris Wilson; Goel, Akash; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support On Thu, Feb 06, 2014 at 11:56

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support

, February 07, 2014 3:11 AM To: Goel, Akash; intel-gfx@lists.freedesktop.org Cc: Goel, Akash Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support akash.g...@intel.com writes: From: Akash Goel akash.g...@intel.com This adds support for using the write-enable bit

Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV.

Please could you kindly elaborate here, it will help us to proceed further with this patch. Best Regards Akash -Original Message- From: Goel, Akash Sent: Monday, January 13, 2014 3:17 PM To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation

message properly. Actually I have reverted the change, enabling of MI_FLUSH, in this new version of the patch, as you also said this is obsolete. Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, February 07, 2014 6:01 PM To: Goel

Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV.

not able to understand that how the 'add_request' will help here. Best Regards Akash -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Friday, February 07, 2014 8:17 PM To: Goel, Akash Cc: 'Chris Wilson'; 'intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support

-Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Sunday, February 09, 2014 4:04 PM To: Goel, Akash Cc: Daniel Vetter; Chris Wilson; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit

[Intel-gfx] Request for feedback : New Panel-fitter property for connectors

. Other use case is the Clone mode, where we can use the composed output of the LFP on the external display, with panel fitter enabled, to avoid GPU composition. Please provide inputs/comments on the same. Best regards Akash -Original Message- From: Goel, Akash Sent: Tuesday, February 18

Re: [Intel-gfx] Request for feedback : New Panel-fitter property for connectors

with horizontal vertical scaling ratios. Please provide suggestions, that how we can extend/reuse the 'scaling_mode' property here. Best regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Wednesday, February 19, 2014 1:58 PM To: Goel, Akash Cc

Re: [Intel-gfx] Request for feedback : New Panel-fitter property for connectors

info, considering the options we have . DRM_MODE_PROP_ENUM DRM_MODE_PROP_RANGE DRM_MODE_PROP_BITMASK DRM_MODE_PROP_BLOB Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, February 20, 2014 1:41 PM To: Ville Syrjälä Cc: Goel, Akash

Re: [Intel-gfx] Request for feedback : New Panel-fitter property for connectors

borders in Display window could be accepted from User. Best Regards Akash -Original Message- From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] Sent: Wednesday, February 26, 2014 7:28 PM To: Goel, Akash Cc: Chris Wilson; intel-gfx@lists.freedesktop.org; G, Pallavi; Kannan, Vandana

[Intel-gfx] Request for feedback : [RFC] Added a new 'window size' property for connector

can be avoided except the PIPESRC programming. This could allow to dynamically flip the frame buffers of different resolution without a modeset. Best regards Akash -Original Message- From: Goel, Akash Sent: Tuesday, March 04, 2014 3:42 PM To: intel-gfx@lists.freedesktop.org Cc: Goel

Re: [Intel-gfx] Request for feedback : [RFC] Added a new 'window size' property for connector

shouldn't sprinkle special cases here and there. Sorry but actually I meant to have this check in modeset compute function only. Best regards Akash -Original Message- From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] Sent: Friday, March 07, 2014 2:58 PM To: Goel, Akash Cc: Chris

Re: [Intel-gfx] Request for feedback : [RFC] Added a new 'window size' property for connector

To: Goel, Akash Cc: Chris Wilson; intel-gfx@lists.freedesktop.org; G, Pallavi; Purushothaman, Vijay A Subject: Re: Request for feedback : [RFC] Added a new 'window size' property for connector On Fri, Mar 07, 2014 at 12:45:26PM +, Goel, Akash wrote: Thanks for your feedback. No, fb_id

Re: [Intel-gfx] Request for feedback : [RFC] Added a new 'window size' property for connector

07, 2014 7:41 PM To: Goel, Akash Cc: Chris Wilson; intel-gfx@lists.freedesktop.org; G, Pallavi; Purushothaman, Vijay A; Barstow, Jason; dri-de...@lists.freedesktop.org Subject: Re: Request for feedback : [RFC] Added a new 'window size' property for connector [ccing dri-devel so other people can

Re: [Intel-gfx] [PATCH 0/3] Two new drm crtc properties

Sorry, will send across the corresponding IGT test case also shortly. Best regards Akash -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Monday, March 10, 2014 10:44 AM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re

Re: [Intel-gfx] [PATCH v2 0/3] Two new drm crtc properties

Hi Ville, Please could you review this patch provide a feedback. This is as per your suggestions our earlier discussions. Regards, Sourab -Original Message- From: Goel, Akash Sent: Tuesday, March 11, 2014 6:24 PM To: intel-gfx@lists.freedesktop.org Cc: Purushothaman, Vijay A; G

Re: [Intel-gfx] [PATCH 0/3] Two new drm crtc properties

...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Saturday, March 22, 2014 1:24 AM To: Goel, Akash Cc: intel-gfx Subject: Re: [Intel-gfx] [PATCH 0/3] Two new drm crtc properties On Mon, Mar 10, 2014 at 6:14 AM, Daniel Vetter dan...@ffwll.ch wrote: On Mon, Mar 10, 2014 at 10:40:50AM +0530, akash.g

Re: [Intel-gfx] [PATCH v4 3/3] drm/i915: New drm crtc property for varying the size of borders

Hi Ville, Please could you review this patch. Best Regards Akash -Original Message- From: Goel, Akash Sent: Wednesday, March 26, 2014 9:25 AM To: intel-gfx@lists.freedesktop.org Cc: Purushothaman, Vijay A; G, Pallavi; Goel, Akash Subject: [PATCH v4 3/3] drm/i915: New drm crtc property

Re: [Intel-gfx] [PATCH v3] drm/i915: Added write-enable pte bit support

Hi Chris, Gentle reminder, Please can you review this patch, have address the review comments. Best Regards Akash -Original Message- From: Goel, Akash Sent: Tuesday, February 11, 2014 2:19 PM To: intel-gfx@lists.freedesktop.org Cc: Goel, Akash Subject: [PATCH v3] drm/i915: Added write

Re: [Intel-gfx] [PATCH 1/7] drm/i915/skl: Added new macros

Thanks for the review. Agree it's not an appropriate name. Please kindly suggest one. 'GT_TIME_COUNTER_UNITS_FROM_PERIOD' ?? Best regards Akash -Original Message- From: Lespiau, Damien Sent: Tuesday, February 17, 2015 8:10 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] [PATCH 1/7] drm/i915/skl: Added new macros

Will prefer GT_INTERVAL_FROM_US, as GT_EVALUATION_COUNTER_FROM_US would be more specific. Best regards Akash -Original Message- From: Lespiau, Damien Sent: Tuesday, February 17, 2015 8:56 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/7] drm/i915/skl

Re: [Intel-gfx] [PATCH v6 05/19] drm/i915/gen8: Add dynamic page trace events

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: The dynamic page allocation patch series added it for GEN6, this patch adds them for GEN8. v2: Consolidate pagetable/page_directory events v3: Multiple rebases. v4:

Re: [Intel-gfx] [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure

On 7/29/2015 9:53 PM, Michel Thierry wrote: Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when i915.enable_ppgtt = 3. v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt

Re: [Intel-gfx] [PATCH v6 08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support

On 7/29/2015 9:53 PM, Michel Thierry wrote: In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains the base address to PML4, while the other PDP registers are ignored. In LRC, the addressing mode must be specified in every context descriptor, and the base address to PML4 is

Re: [Intel-gfx] [PATCH v6 01/19] drm/i915: Remove unnecessary gen8_clamp_pd

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: gen8_clamp_pd clamps to the next page directory boundary, but the macro gen8_for_each_pde already has a check to stop at the page directory boundary. Furthermore,

Re: [Intel-gfx] [PATCH v6 09/19] drm/i915/gen8: Pass sg_iter through pte inserts

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: As a step towards implementing 4 levels, while not discarding the existing pte insert functions, we need to pass the sg_iter through. The current function understands to

Re: [Intel-gfx] [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: This transitional patch doesn't do much for the existing code. However, it should make upcoming patches to use the full 48b address space a bit easier. v2: Renamed

Re: [Intel-gfx] [PATCH v6 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT

On 7/29/2015 9:53 PM, Michel Thierry wrote: The insert_entries function was the function used to write PTEs. For the PPGTT it was hardcoded to only understand two level page tables, which was the case for GEN7. We can reuse this for 4 level page tables, and remove the concept of insert_entries,

Re: [Intel-gfx] [PATCH v6 11/19] drm/i915/gen8: Initialize PDPs and PML4

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: Similar to PDs, while setting up a page directory pointer, make all entries of the pdp point to the scratch pd before mapping (and make all its entries point to the

Re: [Intel-gfx] [PATCH v6 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to.

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Support for pread/pwrite from/to non shmem backed objects

On 7/22/2015 8:09 PM, Chris Wilson wrote: On Wed, Jul 22, 2015 at 07:21:49PM +0530, ankitprasad.r.sha...@intel.com wrote: static int i915_gem_shmem_pread(struct drm_device *dev, struct drm_i915_gem_object *obj, @@ -754,17 +850,20 @@ i915_gem_pread_ioctl(struct

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add support for stealing purgable stolen pages

On 7/27/2015 3:08 PM, Daniel Vetter wrote: On Wed, Jul 22, 2015 at 07:21:48PM +0530, ankitprasad.r.sha...@intel.com wrote: From: Chris Wilson chris at chris-wilson.co.uk If we run out of stolen memory when trying to allocate an object, see if we can reap enough purgeable objects to free up

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add support for stealing purgable stolen pages

On 7/31/2015 8:36 PM, Chris Wilson wrote: On Fri, Jul 31, 2015 at 08:12:30PM +0530, Goel, Akash wrote: On 7/29/2015 5:34 PM, Chris Wilson wrote: On Mon, Jul 27, 2015 at 11:38:13AM +0200, Daniel Vetter wrote: Chris and I just discussed on irc that the bound_list isn't in a great LRU order

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add support for stealing purgable stolen pages

On 7/29/2015 5:34 PM, Chris Wilson wrote: On Mon, Jul 27, 2015 at 11:38:13AM +0200, Daniel Vetter wrote: Chris and I just discussed on irc that the bound_list isn't in a great LRU order right now and Chris sent out a fix for that. But it only works if we preferrentially shrink inactive

Re: [Intel-gfx] [PATCH v8 18/19] drm/i915/gen8: Flip the 48b switch

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/31/2015 6:05 PM, Michel Thierry wrote: Use 48b addresses if hw supports it (i915.enable_ppgtt=3). Update the sanitize_enable_ppgtt for 48 bit PPGTT mode. Note, aliasing PPGTT remains 32b only. v2:

Re: [Intel-gfx] [PATCH v8 06/19] drm/i915/gen8: Add PML4 structure

On 7/31/2015 5:42 PM, Michel Thierry wrote: Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when i915.enable_ppgtt = 3. v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt

Re: [Intel-gfx] [PATCH v7 08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/30/2015 3:36 PM, Michel Thierry wrote: In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains the base address to PML4, while the other PDP registers are ignored. In LRC, the addressing mode

Re: [Intel-gfx] [PATCH v7 07/19] drm/i915/gen8: implement alloc/free for 4lvl

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/30/2015 3:35 PM, Michel Thierry wrote: PML4 has no special attributes, and there will always be a PML4. So simply initialize it at creation, and destroy it at the end. The code for 4lvl is able to call into

Re: [Intel-gfx] [PATCH v7 06/19] drm/i915/gen8: Add PML4 structure

On 7/30/2015 3:34 PM, Michel Thierry wrote: Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when i915.enable_ppgtt = 3. v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt

Re: [Intel-gfx] [PATCH v7 03/19] drm/i915/gen8: Abstract PDP usage

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/30/2015 3:32 PM, Michel Thierry wrote: Up until now, ppgtt-pdp has always been the root of our page tables. Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs. In preparation for 4 level page tables,

Re: [Intel-gfx] [PATCH v7 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/30/2015 3:32 PM, Michel Thierry wrote: The insert_entries function was the function used to write PTEs. For the PPGTT it was hardcoded to only understand two level page tables, which was the case for GEN7. We

Re: [Intel-gfx] [PATCH v9 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 8/3/2015 2:23 PM, Michel Thierry wrote: When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to.

Re: [Intel-gfx] [PATCH v9 06/19] drm/i915/gen8: Add PML4 structure

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 8/3/2015 2:22 PM, Michel Thierry wrote: Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when

Re: [Intel-gfx] [PATCH v6 15/19] drm/i915: batch_obj vm offset must be u64

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: Otherwise it can overflow in 48-bit mode, and cause an incorrect exec_start. Before commit 5f19e2bffa63a91cd4ac1adcec648e14a44277ce (drm/i915: Merged the many

Re: [Intel-gfx] [PATCH v6 16/19] drm/i915/userptr: Kill user_size limit check

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:54 PM, Michel Thierry wrote: GTT was only 32b and its max value is 4GB. In order to allow objects bigger than 4GB in 48b PPGTT, i915_gem_userptr_ioctl we could check against max 48b range (1ULL 48).

Re: [Intel-gfx] [PATCH v6 12/19] drm/i915: Expand error state's address width to 64b

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: v2: For semaphore errors, object is mapped to GGTT and offset will not be 4GB, print only lower 32-bits (Akash) v3: Print gtt_offset in groups of 32-bit (Chris) Cc:

Re: [Intel-gfx] [PATCH v6 13/19] drm/i915/gen8: Add ppgtt info and debug_dump

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: v2: Clean up patch after rebases. v3: gen8_dump_ppgtt for 32b and 48b PPGTT. v4: Use used_pml4es/pdpes (Akash). v5: Rebase after Mika's ppgtt cleanup / scratch merge patch

Re: [Intel-gfx] [PATCH v6 14/19] drm/i915: object size needs to be u64

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:53 PM, Michel Thierry wrote: In a 48b world, users can try to allocate buffers bigger than 4GB; in these cases it is important that size is a 64b variable. v2: Drop the warning about bind with size

Re: [Intel-gfx] [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset Wa32bitInstructionBaseOffset

Reviewed the patch it looks fine. Reviewed-by: Akash Goel akash.g...@intel.com On 7/29/2015 9:54 PM, Michel Thierry wrote: There are some allocations that must be only referenced by 32-bit offsets. To limit the chances of having the first 4GB already full, objects not requiring this workaround

Re: [Intel-gfx] [PATCH v6 18/19] drm/i915/gen8: Flip the 48b switch

On 7/29/2015 9:54 PM, Michel Thierry wrote: Use 48b addresses if hw supports it (i915.enable_ppgtt=3). Note, aliasing PPGTT remains 32b only. Signed-off-by: Michel Thierry michel.thie...@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--- drivers/gpu/drm/i915/i915_params.c | 2

Re: [Intel-gfx] [PATCH] drm/i915: Only move to the CPU write domain if keeping the GTT pages

in the future (i.e. I915_MADV_WILLNEED pages) we can simply treat a live CPU mmaping as a special case of WILLNEED (which it is!). Any I915_MADV_DONTNEED pages and their mmapings are shotdown immediately following put_pages. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Goel, Akash

Re: [Intel-gfx] [PATCH] drm/i915: Only move to the CPU write domain if keeping the GTT pages

On 8/9/2015 4:25 PM, Chris Wilson wrote: On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote: On 8/7/2015 1:37 PM, Daniel Vetter wrote: I presume though you only want to avoid clflush when actually purging an object, so maybe we can keep this by purging the shmem backing node first

Re: [Intel-gfx] [PATCH] drm/i915: Only move to the CPU write domain if keeping the GTT pages

On 8/9/2015 6:19 PM, Chris Wilson wrote: On Sun, Aug 09, 2015 at 05:11:52PM +0530, Goel, Akash wrote: On 8/9/2015 4:25 PM, Chris Wilson wrote: On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote: On 8/7/2015 1:37 PM, Daniel Vetter wrote: I presume though you only want to avoid

Re: [Intel-gfx] [PATCH v5 17/19] drm/i915: Wa32bitGeneralStateOffset Wa32bitInstructionBaseOffset

On 7/16/2015 3:03 PM, Michel Thierry wrote: There are some allocations that must be only referenced by 32-bit offsets. To limit the chances of having the first 4GB already full, objects not requiring this workaround use DRM_MM_SEARCH_BELOW/ DRM_MM_CREATE_TOP flags In specific, any resource

Re: [Intel-gfx] [PATCH v4] drm/i915: Add soft-pinning API for execbuffer

On 6/30/2015 7:50 PM, Daniel, Thomas wrote: Many apologies to Michal for incorrectly spelling his name in the CC list. Thomas. -Original Message- From: Daniel, Thomas Sent: Tuesday, June 30, 2015 3:13 PM To: intel-gfx@lists.freedesktop.org Cc: Chris Wilson; Goel, Akash; Belgaumkar

Re: [Intel-gfx] [PATCH v6] drm/i915: Add soft-pinning API for execbuffer

Discussed sometime back about this patch with Chris. He mainly has 2 concerns with it. 1. The linear walk used by the patch to detect the overlapping objects would be expensive. 2. Restriction to disallow !RCS submissions for non-default contexts, which could lead to lot of conflicts for the

Re: [Intel-gfx] [PATCH v3 02/17] drm/i915/gen8: Make pdp allocation more dynamic

On 7/1/2015 8:57 PM, Michel Thierry wrote: This transitional patch doesn't do much for the existing code. However, it should make upcoming patches to use the full 48b address space a bit easier. The patch also introduces the PML4, ie. the new top level structure of the page tables. Would be

Re: [Intel-gfx] [PATCH v3 09/17] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

On 7/1/2015 8:57 PM, Michel Thierry wrote: When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to. Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range. This patch was

Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Expand error state's address width to 64b

On 7/1/2015 8:57 PM, Michel Thierry wrote: Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Michel Thierry michel.thie...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gpu_error.c | 17 + 2 files changed, 11

Re: [Intel-gfx] [PATCH v3 03/17] drm/i915/gen8: Abstract PDP usage

On 7/1/2015 8:57 PM, Michel Thierry wrote: Up until now, ppgtt-pdp has always been the root of our page tables. Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs. In preparation for 4 level page tables, we need to stop use ppgtt-pdp directly unless we know it's what we want. The

Re: [Intel-gfx] [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl

On 7/1/2015 8:57 PM, Michel Thierry wrote: PML4 has no special attributes, and there will always be a PML4. So simply initialize it at creation, and destroy it at the end. The code for 4lvl is able to call into the existing 3lvl page table code to handle all of the lower levels. v2: Return

Re: [Intel-gfx] [PATCH v3 12/17] drm/i915/gen8: Add ppgtt info and debug_dump

On 7/1/2015 8:57 PM, Michel Thierry wrote: v2: Clean up patch after rebases. v3: gen8_dump_ppgtt for 32b and 48b PPGTT. v4: Use used_pml4es/pdpes (Akash). v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series. Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Michel

Re: [Intel-gfx] [PATCH] drm/i915: Unbind objects in shrinker only if device is runtime active

On 12/24/2015 5:52 PM, Chris Wilson wrote: On Thu, Dec 24, 2015 at 04:16:08PM +0530, Praveen Paneri wrote: When the system is running low on memory, gem shrinker is invoked. In this process objects will be unbounded from GTT and unbinding process will require access to GTT(GTTADR) and also to

Re: [Intel-gfx] [PATCH] drm/i915: Unbind objects in shrinker only if device is runtime active

On 12/24/2015 8:02 PM, Chris Wilson wrote: On Thu, Dec 24, 2015 at 07:54:09PM +0530, Goel, Akash wrote: On 12/24/2015 5:52 PM, Chris Wilson wrote: On Thu, Dec 24, 2015 at 04:16:08PM +0530, Praveen Paneri wrote: When the system is running low on memory, gem shrinker is invoked

Re: [Intel-gfx] [PATCH] drm/i915 : Avoid superfluous invalidation of CPU cache lines

On 11/25/2015 10:58 PM, Chris Wilson wrote: On Wed, Nov 25, 2015 at 01:02:20PM +0200, Ville Syrjälä wrote: On Tue, Nov 24, 2015 at 10:39:38PM +, Chris Wilson wrote: On Tue, Nov 24, 2015 at 07:14:31PM +0100, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 12:04:06PM +0200, Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915 : Avoid superfluous invalidation of CPU cache lines

On 11/25/2015 2:51 PM, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 10:39:38PM +, Chris Wilson wrote: On Tue, Nov 24, 2015 at 07:14:31PM +0100, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 12:04:06PM +0200, Ville Syrjälä wrote: On Tue, Nov 24, 2015 at 03:35:24PM +0530,

Re: [Intel-gfx] [PATCH] drm/i915: Disable shrinker for non-swapped backed objects

On 11/25/2015 3:28 PM, Chris Wilson wrote: On Wed, Nov 25, 2015 at 10:17:49AM +0100, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 11:17:38PM +, Chris Wilson wrote: On Tue, Nov 24, 2015 at 06:15:47PM +0100, Daniel Vetter wrote: On Mon, Nov 23, 2015 at 09:20:24AM +, Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915 : Avoid superfluous invalidation of CPU cache lines

On 11/25/2015 3:30 PM, Daniel Vetter wrote: On Wed, Nov 25, 2015 at 02:57:47PM +0530, Goel, Akash wrote: On 11/25/2015 2:51 PM, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 10:39:38PM +, Chris Wilson wrote: On Tue, Nov 24, 2015 at 07:14:31PM +0100, Daniel Vetter wrote: On Tue, Nov 24

Re: [Intel-gfx] [PATCH] drm/i915 : Avoid superfluous invalidation of CPU cache lines

On 11/30/2015 1:45 PM, Daniel Vetter wrote: On Mon, Nov 30, 2015 at 11:54:14AM +0530, Goel, Akash wrote: On 11/25/2015 3:30 PM, Daniel Vetter wrote: On Wed, Nov 25, 2015 at 02:57:47PM +0530, Goel, Akash wrote: On 11/25/2015 2:51 PM, Daniel Vetter wrote: On Tue, Nov 24, 2015 at 10:39

Re: [Intel-gfx] [PATCH v3] drm/i915 : Avoid superfluous invalidation of CPU cache lines

On 12/1/2015 7:30 PM, Ville Syrjälä wrote: On Tue, Dec 01, 2015 at 01:49:10PM +, Chris Wilson wrote: On Tue, Dec 01, 2015 at 03:28:28PM +0200, Ville Syrjälä wrote: On Tue, Dec 01, 2015 at 01:09:33PM +, Chris Wilson wrote: On Tue, Dec 01, 2015 at 02:34:41PM +0200, Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Support to enable TRTT on GEN9

On 1/10/2016 11:09 PM, Chris Wilson wrote: On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote: From: Akash Goel Gen9 has an additional address translation hardware support in form of Tiled Resource Translation Table (TR-TT) which provides an extra

Re: [Intel-gfx] [RFC 00/12] Support for sustained capturing of GuC firmware logs

On 6/3/2016 12:45 PM, Daniel Vetter wrote: On Thu, Jun 02, 2016 at 12:21:49PM +0200, Johannes Berg wrote: On Thu, 2016-06-02 at 10:16 +, Daniel Vetter wrote: I still kinda like relayfs, except that it's not available in non- debug builds. But so are plenty of other really interesting

Re: [Intel-gfx] [RFC 09/12] drm/i915: Add a char device file interface to capture GuC ukernel logs

On 5/28/2016 1:18 AM, Chris Wilson wrote: On Sat, May 28, 2016 at 01:13:00AM +0530, akash.g...@intel.com wrote: From: Akash Goel This patch provides a new character device file interface '/dev/dri/guc_log' for the User to capture the GuC ukernel logs. Do not make the

Re: [Intel-gfx] [RFC 03/12] drm/i915: Support for GuC interrupts

On 5/28/2016 1:13 AM, Chris Wilson wrote: On Sat, May 28, 2016 at 01:12:54AM +0530, akash.g...@intel.com wrote: From: Sagar Arun Kamble There are certain types of interrupts which Host can recieve from GuC. GuC ukernel sends an interrupt to Host for certain events,

Re: [Intel-gfx] [RFC 03/12] drm/i915: Support for GuC interrupts

On 5/28/2016 1:26 AM, Chris Wilson wrote: On Sat, May 28, 2016 at 01:12:54AM +0530, akash.g...@intel.com wrote: From: Sagar Arun Kamble There are certain types of interrupts which Host can recieve from GuC. GuC ukernel sends an interrupt to Host for certain events,

Re: [Intel-gfx] [RFC 03/12] drm/i915: Support for GuC interrupts

On 5/28/2016 5:43 PM, Chris Wilson wrote: On Sat, May 28, 2016 at 02:52:16PM +0530, Goel, Akash wrote: On 5/28/2016 1:26 AM, Chris Wilson wrote: On Sat, May 28, 2016 at 01:12:54AM +0530, akash.g...@intel.com wrote: From: Sagar Arun Kamble <sagar.a.kam...@intel.com> There are c

Re: [Intel-gfx] [RFC 03/12] drm/i915: Support for GuC interrupts

On 5/28/2016 8:05 PM, Chris Wilson wrote: On Sat, May 28, 2016 at 07:15:52PM +0530, Goel, Akash wrote: On 5/28/2016 5:43 PM, Chris Wilson wrote: On Sat, May 28, 2016 at 02:52:16PM +0530, Goel, Akash wrote: On 5/28/2016 1:26 AM, Chris Wilson wrote: On Sat, May 28, 2016 at 01:12:54AM

Re: [Intel-gfx] [PATCH] drm/i915: Support to enable TRTT on GEN9

On 1/11/2016 2:19 PM, Chris Wilson wrote: On Mon, Jan 11, 2016 at 01:09:50PM +0530, Goel, Akash wrote: On 1/10/2016 11:09 PM, Chris Wilson wrote: On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote: From: Akash Goel <akash.g...@intel.com> Gen9 has an additional a

Re: [Intel-gfx] [PATCH 09/11] drm/i915: New module param to control the size of buffer used for storing GuC firmware logs

On 6/27/2016 7:01 PM, Jani Nikula wrote: On Mon, 27 Jun 2016, akash.g...@intel.com wrote: From: Akash Goel On recieving the log buffer flush interrupt from GuC firmware, Driver stores the snapshot of the log buffer in a local buffer, from which Userspace can pull the

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Decouple GuC log setup from verbosity parameter

On 6/27/2016 8:30 PM, Tvrtko Ursulin wrote: On 27/06/16 13:16, akash.g...@intel.com wrote: From: Sagar Arun Kamble GuC Log buffer allocation was tied up with verbosity level kernel parameter i915.guc_log_level. User could be given a provision to enable logging at

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set

On 6/27/2016 9:16 PM, Tvrtko Ursulin wrote: On 27/06/16 13:16, akash.g...@intel.com wrote: From: Akash Goel So far PM IER/IIR/IMR registers were being used only for Turbo related interrupts. But interrupts coming from GuC also use the same set. As a precursor to

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Decouple GuC log setup from verbosity parameter

On 6/27/2016 9:26 PM, Tvrtko Ursulin wrote: On 27/06/16 16:32, Goel, Akash wrote: On 6/27/2016 8:30 PM, Tvrtko Ursulin wrote: On 27/06/16 13:16, akash.g...@intel.com wrote: From: Sagar Arun Kamble <sagar.a.kam...@intel.com> GuC Log buffer allocation was tied up with verbosity

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Add a relay backed debugfs interface for capturing GuC logs

On 6/28/2016 3:17 PM, Chris Wilson wrote: On Mon, Jun 27, 2016 at 05:46:53PM +0530, akash.g...@intel.com wrote: +static void guc_remove_log_relay_file(struct intel_guc *guc) +{ + relay_close(guc->log_relay_chan); +} + +static void guc_create_log_relay_file(struct intel_guc *guc) +{ +

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set

On 6/28/2016 2:05 PM, Tvrtko Ursulin wrote: On 27/06/16 17:35, Goel, Akash wrote: On 6/27/2016 9:16 PM, Tvrtko Ursulin wrote: On 27/06/16 13:16, akash.g...@intel.com wrote: From: Akash Goel <akash.g...@intel.com> So far PM IER/IIR/IMR registers were being used only for Turbo r

Re: [Intel-gfx] [PATCH 10/11] drm/i915: Support to create write combined type vmaps

On 6/28/2016 3:22 PM, Chris Wilson wrote: On Mon, Jun 27, 2016 at 05:46:57PM +0530, akash.g...@intel.com wrote: From: Chris Wilson diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 20c701c..3ef1ee5 100644 ---

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Support for GuC interrupts

On 6/28/2016 3:33 PM, Tvrtko Ursulin wrote: On 27/06/16 13:16, akash.g...@intel.com wrote: From: Sagar Arun Kamble There are certain types of interrupts which Host can recieve from GuC. GuC ukernel sends an interrupt to Host for certain events, like for example

Re: [Intel-gfx] [PATCH] igt/gem_trtt: Exercise the TRTT hardware

On 1/11/2016 6:02 PM, Chris Wilson wrote: On Sat, Jan 09, 2016 at 05:01:30PM +0530, akash.g...@intel.com wrote: +static void* mmap_bo(int fd, uint32_t handle, uint64_t size) +{ + uint32_t *ptr = gem_mmap__cpu(fd, handle, 0, size, PROT_READ); + gem_set_domain(fd, handle,

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On 3/9/2016 9:51 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 09:26:08PM +0530, Goel, Akash wrote: On 3/9/2016 8:32 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: What locks are we holding here? + else if (args->size < sizeof(trtt_

Re: [Intel-gfx] [PATCH v6] igt/gem_trtt: Exercise the TRTT hardware

On 3/18/2016 4:02 PM, Chris Wilson wrote: On Fri, Mar 18, 2016 at 03:22:51PM +0530, Goel, Akash wrote: On 3/18/2016 2:52 PM, Chris Wilson wrote: On Fri, Mar 18, 2016 at 02:31:23PM +0530, Goel, Akash wrote: Hopefully final comments! Missed EINTR handling during evict, If you repeat

Re: [Intel-gfx] [PATCH v6] igt/gem_trtt: Exercise the TRTT hardware

On 3/18/2016 2:06 PM, Chris Wilson wrote: On Fri, Mar 18, 2016 at 02:07:40PM +0530, akash.g...@intel.com wrote: +/* emit_store_qword + * populate batch buffer with MI_STORE_DWORD_IMM command + * @fd: drm file descriptor + * @cmd_buf: batch buffer + * @dw_offset: write offset in batch buffer +

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On 3/9/2016 8:32 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: What locks are we holding here? + else if (args->size < sizeof(trtt_params)) + return -EINVAL; + else if (copy_from_user(_

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