On 4/17/2018 12:18 AM, Gaurav K Singh wrote:
On Geminilake, sometimes audio card is not getting
detected after reboot. This is a spurious issue happening on
Geminilake. HW codec and HD audio controller link was going
out of sync for which there was a fix in i915 driver but
was not getting invok
On 4/17/2018 12:06 PM, Abhay Kumar wrote:
In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This change will ensure CD clock to be twice of BCLK.
v2:
- Address comment (Jani)
- New design approach
v3: -
On 4/18/2018 8:41 AM, Ville Syrjälä wrote:
On Wed, Apr 18, 2018 at 01:49:23PM +0300, Jani Nikula wrote:
On Tue, 17 Apr 2018, "Kumar, Abhay" wrote:
On 4/17/2018 12:06 PM, Abhay Kumar wrote:
In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup.
This res
On 5/1/2018 2:15 AM, Saarinen, Jani wrote:
HI,
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Du,Wenkai
Sent: maanantai 30. huhtikuuta 2018 21.23
To: Kumar, Abhay ; intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani
Subject: Re: [Intel
+ Ville
On 5/1/2018 4:42 PM, Kumar, Abhay wrote:
On 5/1/2018 2:15 AM, Saarinen, Jani wrote:
HI,
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Du,Wenkai
Sent: maanantai 30. huhtikuuta 2018 21.23
To: Kumar, Abhay;intel-gfx
On 5/2/2018 8:12 AM, Ville Syrjälä wrote:
On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
From: me
mostly
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
Signed-off-by
On 5/2/2018 10:14 AM, Ville Syrjälä wrote:
On Wed, May 02, 2018 at 09:57:01AM -0700, Kumar, Abhay wrote:
On 5/2/2018 8:12 AM, Ville Syrjälä wrote:
On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
From: me
mostly
CDCLK has to be at least twice the BLCK regardless of audio
On 5/11/2018 5:33 AM, Ville Syrjälä wrote:
On Wed, May 09, 2018 at 06:25:32PM -0700, Abhay Kumar wrote:
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use a
Hi Ville,
Can we please get this merged to DINQ?
Regards,
Abhay
-Original Message-
From: Du, Wenkai
Sent: Thursday, June 21, 2018 1:16 PM
To: Kumar, Abhay ; intel-gfx@lists.freedesktop.org;
Syrjala, Ville
Cc: Nikula, Jani
Subject: Re: [Intel-gfx] [PATCH v5] drm/i915: Force 2*96
On 8/28/2018 5:39 AM, Ville Syrjälä wrote:
On Mon, Aug 27, 2018 at 11:50:32AM -0700, Abhay Kumar wrote:
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. T
+Susanta
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Kumar, Abhay
Sent: Tuesday, August 28, 2018 5:55 PM
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if
possible
On 8/28
On 3/23/2018 12:21 PM, Kumar, Abhay wrote:
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Wednesday, February 14, 2018 10:00 AM
To: Kumar, Abhay ; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: set minimum CD clock to twice
On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:
On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:
On Sun, 08 Apr 2018, Gaurav K Singh wrote:
On Geminilake, sometimes audio card is not getting
detected after reboot. This is a spurious issue happening on
Geminilake. HW codec and HD audio
On 4/9/2018 3:33 AM, Ville Syrjälä wrote:
On Fri, Apr 06, 2018 at 04:47:08PM +0300, Jani Nikula wrote:
On Thu, 05 Apr 2018, Abhay Kumar wrote:
In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure
On 4/9/2018 4:20 PM, Pandiyan, Dhinakaran wrote:
On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote:
On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:
On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:
On Sun, 08 Apr 2018, Gaurav K Singh wrote:
On Geminilake, sometimes audio card
On 4/10/2018 1:49 AM, Nikula, Jani wrote:
On Tue, 10 Apr 2018, Jani Nikula wrote:
On Mon, 09 Apr 2018, "Kumar, Abhay" wrote:
Dynamic cdclk is disabled in BIOS/GOP hence gop makes it to highest
clock i.e 316.8. Will attach logs with drm debug enabled in bug.
I am also inclined t
On 6/12/2018 5:13 AM, Ville Syrjälä wrote:
On Tue, Jun 12, 2018 at 12:17:41AM -0700, Abhay Kumar wrote:
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use a
On 6/12/2018 11:09 AM, Saarinen, Jani wrote:
HI,
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Patchwork
Sent: tiistai 12. kesäkuuta 2018 11.38
To: Kumar, Abhay
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✓ Fi.CI.IGT
Hi Ville,
Looks like we have right fix from audio and we will not need powerwell 2
reset workaround when changing cdclk.
we need only one patch in this series to get merged.
drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled.
Regards,
Abhay
On 6/13/2018 11:41 AM, Abhay
+ Wenkai
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Abhay Kumar
Sent: Tuesday, June 19, 2018 3:01 PM
To: intel-gfx@lists.freedesktop.org; Syrjala, Ville
Cc: Nikula, Jani
Subject: [Intel-gfx] [PATCH v5] drm/i915: Force 2*96 MHz cdclk
suspend path.
Will take care of comment in next patchset.
[cid:image001.png@01D130F9.DFFC0300]
-Original Message-
From: Paulo Zanoni [mailto:przan...@gmail.com]
Sent: Monday, December 7, 2015 12:52 PM
To: Kumar, Abhay
Cc: Intel Graphics Development
Subject: Re: [Intel-gfx] [PATCH
Is this something close to what we wanted to optimize for edp resume time and
using wall clock.
-Original Message-
From: Kumar, Abhay
Sent: Tuesday, December 15, 2015 2:17 PM
To: Intel-gfx@lists.freedesktop.org
Cc: Kumar, Abhay
Subject: [PATCH] drm/i915: edp resume/On time optimization
AM
To: Kumar, Abhay
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: edp resume/On time optimization.
On Tue, Dec 15, 2015 at 02:16:38PM -0800, abhay.ku...@intel.com wrote:
> From: Abhay Kumar
>
> Make resume codepath not to wait for panel_power_cycle_dela
Changed the implementation using boottime and removed jiffies. Please review
and let us know if this is close.
-Original Message-
From: Kumar, Abhay
Sent: Friday, December 18, 2015 11:55 AM
To: Intel-gfx@lists.freedesktop.org
Cc: Kumar, Abhay
Subject: [PATCH] drm/i915: edp resume/On
On 1/22/2016 5:39 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
v3
Thanks Daniel. Will push today with proper comment.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Monday, December 21, 2015 7:58 AM
To: Kumar, Abhay
Cc: Intel-gfx@lists.freedesktop.org; Syrjala, Ville; Paulo Zanoni
Subject: Re
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if
this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
Cc: Ville Syrjälä
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/i
On 1/5/2016 3:04 AM, Daniel Vetter wrote:
On Tue, Jan 05, 2016 at 01:30:53AM +, Kumar, Abhay wrote:
Ville,
Is this patch is coming close to what you wanted?
Please don't bottom-post but not quote properly - no one will ever find
your comment and assume you accidentally sent ou
On 12/21/2015 5:18 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
Cc
On 1/7/2016 10:15 AM, Ville Syrjälä wrote:
On Mon, Dec 21, 2015 at 05:18:52PM -0800, abhay.ku...@intel.com wrote:
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remo
On 1/12/2016 5:57 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
v3
On 1/12/2016 5:57 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
v3
On 1/20/2016 5:06 AM, Ville Syrjälä wrote:
On Wed, Jan 20, 2016 at 03:29:00PM +0530, Kumar, Shobhit wrote:
On 01/20/2016 02:30 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2016 at 02:37:55PM -0800, Kumar, Abhay wrote:
On 1/12/2016 5:57 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume
On 1/26/2016 3:36 AM, Ville Syrjälä wrote:
On Sat, Jan 23, 2016 at 08:43:33AM -, Patchwork wrote:
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL
On 1/21/2016 9:48 PM, Kumar, Shobhit wrote:
On 01/21/2016 05:47 PM, Kumar, Abhay wrote:
On 1/20/2016 5:06 AM, Ville Syrjälä wrote:
On Wed, Jan 20, 2016 at 03:29:00PM +0530, Kumar, Shobhit wrote:
On 01/20/2016 02:30 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2016 at 02:37:55PM -0800, Kumar
On 10/30/2017 5:21 PM, Pandiyan, Dhinakaran wrote:
On Sun, 2017-10-29 at 03:04 +, Kumar, Abhay wrote:
+ Subhransu
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Kumar, Abhay
Sent: Thursday, October 26, 2017 12:10 PM
To: Jani
On 10/26/2017 1:45 AM, Jani Nikula wrote:
On Wed, 25 Oct 2017, Dhinakaran Pandiyan wrote:
On Wednesday, October 25, 2017 3:02:12 PM PDT abhay.ku...@intel.com wrote:
From: Abhay Kumar
In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup.
This result in no audio foreve
+ Subhransu
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Kumar, Abhay
Sent: Thursday, October 26, 2017 12:10 PM
To: Jani Nikula ; Dhinakaran Pandiyan
; subransu.s.pru...@intel.com
Cc: intel-gfx@lists.freedesktop.org; Nujella
:17 AM
To: Kumar, Abhay
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/chv: Recomputing CHV watermark.
On Mon, May 11, 2015 at 04:27:40PM -0700, abhay.ku...@intel.com wrote:
> From: Abhay
>
> Current WM calculation is causing regression on SR residency.
>
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