[Intel-gfx] [PATCH] drm/i915/skl: Add check for minimum allocable Display Data Blocks

Fifo Underrun is observed when allocating minimum allocable blocks for any plane, This patch calculate checks for upper lower DDB bound for each plane according to total allocated DDB for that Pipe. Signed-off-by: Kumar, Mahesh mahesh1.ku...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2

[Intel-gfx] [PATCH v2] kms_universal_plane: subtest for yuv pixel format in primary plane

This test commit YUV framebuffer in primay plane. I'm using empty FB, because this fulfills the purpose of testing YUV. V2: Revert chnages for MAX_PLANE count as per nabendu's comment. These changes are already floating for review. Signed-off-by: Kumar, Mahesh mahesh1.ku...@intel.com --- lib

Re: [Intel-gfx] [PATCH V2] drm/i915/skl+: Add YUV pixel format in Capability list

formats. Regards, Sonika -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Kumar, Mahesh Sent: Friday, July 17, 2015 7:21 PM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH V2] drm/i915/skl+: Add YUV pixel format in Capability

[Intel-gfx] [PATCH V2] drm/i915/skl+: Add YUV pixel format in Capability list

by zero error during watermark calculation. V2: Don't break NV12 case. Signed-off-by: Kumar, Mahesh mahesh1.ku...@intel.com Cc: Konduru, Chandra chandra.kond...@intel.com --- IGT changes made for testcase will be sent in separate patch. drivers/gpu/drm/i915/intel_display.c | 4 drivers

[Intel-gfx] [PATCH] drm/i915/skl+: Add YUV pixel format in Capability list

by zero error during watermark calculation. Signed-off-by: Kumar, Mahesh mahesh1.ku...@intel.com Cc: Konduru, Chandra chandra.kond...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 4 drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff

[Intel-gfx] [PATCH] kms_universal_plane: subtest for yuv pixel format in primary plane

This test commit YUV framebuffer in primay plane. I'm using empty FB, because this fulfills the purpose of testing YUV. Increase IGT_MAX_PLANES to 5 and add enum for IGT_PLANE_4, as in Broxton we have 4Plane+1cursor plane. Signed-off-by: Kumar, Mahesh mahesh1.ku...@intel.com --- lib/igt_fb.c

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correct other-pipe watermark update condition check (v2)

Hoping 2-stage watermark programming will take care of this, as in that case, If I'm not misunderstood final results should be stored after calculation for all pipes. Regards, -Mahesh On 10/23/2015 10:11 PM, Matt Roper wrote: From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> If ddb

[Intel-gfx] [PATCH 1/2] drm/i915/skl: Avoid using un-initialized bits_per_pixel

Don't rely on fb->bits_per_pixel as intel_framebuffer_init is not filling bits_per_pixel field of fb-struct for YUV pixel format. This leads to divide by zero error during watermark calculation. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> Cc: Konduru, Chandra <chandra.kond.

[Intel-gfx] [PATCH 2/2] drm/i915/skl+: Add YUV pixel format in Capability list

GEN >= 9 supports YUV format for all planes, but it's not exported in Capability list of primary plane. Add YUV formats in skl_primary_formats list. Testcase: igt/kms_universal_plane.c Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> Cc: Konduru, Chandra <chandra.kond.

[Intel-gfx] [PATCH] drm/i915/skl: Correct other-pipe watermark update condition check

atch corrects this and check if DDB allocation for pipes is changed, then only recalculate watermarks. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

e / 512]/4 : ceiling[plane bytes per line / 512] As per BSpec Don't increment selected "result_blocks" & "result_lines" in case of BROXTON. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 10 -- 1 file changed, 8 insertions(

[Intel-gfx] [PATCH v2 8/9] drm/i915/bxt: set chicken bit as IPC y-tile WA

From: Mahesh Kumar It implements the WA to enable IDLE_WAKEMEM bit of CHICKEN_DCPR_1 register for Broxton platform. When IPC is enabled & Y-tile is enabled in any of the enabled plane, above bit should be set. Without this WA system observes random hang. Signed-off-by:

[Intel-gfx] [PATCH v2 9/9] drm/i915/bxt: Implement Transition WM

From: Mahesh Kumar This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to decide, number of blocks to be fetched before reducing the priority of display to fetch from memory. Changes since v1: - Don't enable transition WM for

[Intel-gfx] [PATCH v2 2/9] drm/i915/skl+: use linetime latency instead of ddb size

From: Mahesh Kumar This patch make changes to use linetime latency instead of allocated DDB size during plane watermark calculation in switch case, This is required to implement new DDB allocation algorithm. In New Algorithm DDB is allocated based on WM values, because

[Intel-gfx] [PATCH v2 3/9] drm/i915/skl: New ddb allocation algorithm

From: Mahesh Kumar This patch implements new DDB allocation algorithm as per HW team suggestion. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of enabling

[Intel-gfx] [PATCH v2 6/9] drm/i915/skl+: change WM calc to fixed point 16.16

From: Mahesh Kumar This patch changes Watermak calculation to fixed point calculation. Problem with current calculation is during plane_blocks_per_line calculation we divide intermediate blocks with min_scanlines and takes floor of the result because of integer

[Intel-gfx] [PATCH v2 0/9] New DDB Algo and WM fixes

From: Mahesh Kumar This series implements new DDB allocation algorithm to solve the cases, where we have sufficient DDB available to enable multiple planes, But due to the current algorithm not dividing it properly among planes, we end-up failing the flip. It also takes

[Intel-gfx] [PATCH v2 5/9] drm/i915/gen9: WM memory bandwidth related workaround

From: Mahesh Kumar This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Changes since v1: - Rebase on top of Paulo's patch series Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v2 4/9] drm/i915: Decode system memory bandwidth

From: Mahesh Kumar This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 96

[Intel-gfx] [PATCH v2 7/9] drm/i915/bxt: Enable IPC support

From: Mahesh Kumar This patch adds IPC support for platforms. This patch enables IPC only for BXT platform as for SKL recommendation is to keep is disabled This patch also adds kernel command-line option to enable/disable the IPC if required. Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v2 1/9] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions

From: Mahesh Kumar This patch make use of plane_wm variable directly instead of passing skl_plane_wm struct. this way reduces number of argument requirement in watermark calculation functions. It also gives more freedom of decision making to implement Bspec WM

[Intel-gfx] [PATCH v4] drm/i915/bxt: Implement Transition WM

From: Mahesh Kumar This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to decide, number of blocks to be fetched before reducing the priority of display to fetch from memory. Changes since v1: - Don't enable transition WM for

[Intel-gfx] [PATCH v4] drm/i915/skl: New ddb allocation algorithm

From: Mahesh Kumar This patch implements new DDB allocation algorithm as per HW team suggestion. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of enabling

[Intel-gfx] [PATCH v3 8/9] drm/i915/bxt: set chicken bit as IPC y-tile WA

From: Mahesh Kumar It implements the WA to enable IDLE_WAKEMEM bit of CHICKEN_DCPR_1 register for Broxton platform. When IPC is enabled & Y-tile is enabled in any of the enabled plane, above bit should be set. Without this WA system observes random hang. Signed-off-by:

[Intel-gfx] [PATCH v3 0/9] New DDB Algo and WM fixes

From: Mahesh Kumar This series implements new DDB allocation algorithm to solve the cases, where we have sufficient DDB available to enable multiple planes, But due to the current algorithm not dividing it properly among planes, we end-up failing the flip. It also takes

[Intel-gfx] [PATCH v3 5/9] drm/i915/gen9: WM memory bandwidth related workaround

From: Mahesh Kumar This patch implemnets Workarounds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Changes since v1: - Rebase on top of Paulo's patch series Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v3 1/9] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions

From: Mahesh Kumar This patch make use of plane_wm variable directly instead of passing skl_plane_wm struct. this way reduces number of argument requirement in watermark calculation functions. It also gives more freedom of decision making to implement Bspec WM

[Intel-gfx] [PATCH v3 9/9] drm/i915/bxt: Implement Transition WM

From: Mahesh Kumar This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to decide, number of blocks to be fetched before reducing the priority of display to fetch from memory. Changes since v1: - Don't enable transition WM for

[Intel-gfx] [PATCH v3 3/9] drm/i915/skl: New ddb allocation algorithm

From: Mahesh Kumar This patch implements new DDB allocation algorithm as per HW team suggestion. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of enabling

[Intel-gfx] [PATCH v3 2/9] drm/i915/skl+: use linetime latency instead of ddb size

From: Mahesh Kumar This patch make changes to use linetime latency instead of allocated DDB size during plane watermark calculation in switch case, This is required to implement new DDB allocation algorithm. In New Algorithm DDB is allocated based on WM values, because

[Intel-gfx] [PATCH v3 4/9] drm/i915: Decode system memory bandwidth

From: Mahesh Kumar This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 96

[Intel-gfx] [PATCH v3 7/9] drm/i915/bxt: Enable IPC support

From: Mahesh Kumar This patch adds IPC support for platforms. This patch enables IPC only for BXT platform as for SKL recommendation is to keep is disabled This patch also adds kernel command-line option to enable/disable the IPC if required. Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v3 6/9] drm/i915/skl+: change WM calc to fixed point 16.16

From: Mahesh Kumar This patch changes Watermak calculation to fixed point calculation. Problem with current calculation is during plane_blocks_per_line calculation we divide intermediate blocks with min_scanlines and takes floor of the result because of integer

[Intel-gfx] [PATCH] FOR_UPSTREAM [VPG]: drm/i915/skl+: Implement Transition WM

This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to decide, number of blocks to be fetched before reducing the priority of display to fetch from memory. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.

[Intel-gfx] [PATCH 2/7] drm/i915/skl+: use linetime latency instead of ddb size

will not be available during WM calculation, So this "linetime latency" is suggested by SV/HW team to use during switch-case for WM blocks selection. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 5 - 1 file changed, 4 insertions(+), 1 deletio

[Intel-gfx] [PATCH 1/7] drm/i915/hsw+: set intel_crtc active once pipe is active

Set the intel_crtc->active flag after pipe/crtc is actually active in haswell_crtc_enable function. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 5/7] drm/i915: Decode system memory bandwidth

This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.

[Intel-gfx] [PATCH 0/7] Implement New DDB allocation algorithm

vailable then the best cases allocation is to enable Level2 which requires 168 blocks Kumar, Mahesh (7): drm/i915/hsw+: set intel_crtc active once pipe is active drm/i915/skl+: use linetime latency instead of ddb size drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions drm/

[Intel-gfx] [PATCH] drm/i915/gen9: WM memory bandwidth related workaround

This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 9 +++ drivers/gpu/drm/i915/intel_drv.h | 11 +++ drive

[Intel-gfx] [PATCH 3/7] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions

This patch make use of plane_wm variable directly instead of passing skl_plane_wm struct. this way reduces number of argument requirement in watermark calculation functions. It also gives more freedom of decision making to implement Bspec WM workarounds. Signed-off-by: Kumar, Mahesh <mahesh1

[Intel-gfx] [PATCH 4/7] drm/i915/skl: New ddb allocation algorithm

, for efficient power saving. Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 129 +--- 1 file changed, 67 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5

[Intel-gfx] [PATCH v4 0/8] New DDB Algo and WM fixes

Drop Transition WM and patch to reduce function parameter patch - split patches Kumar, Mahesh (3): drm/i915/skl+: use linetime latency instead of ddb size drm/i915: Decode system memory bandwidth drm/i915/gen9: WM memory bandwidth related workaround Mahesh Kumar (5): drm/i915/skl: New ddb al

[Intel-gfx] [PATCH v4 1/8] drm/i915/skl+: use linetime latency instead of ddb size

will not be available during WM calculation, So this "linetime latency" is suggested by SV/HW team to use during switch-case for WM blocks selection. Changes since v1: - Rebase on top of Paulo's patch series Changes since v2: - Fix if-else condition (pointed by Maarten) Signed-off-by: "Kumar, M

[Intel-gfx] [PATCH v4 8/8] drm/i915/bxt: Enable IPC support

From: Mahesh Kumar This patch adds IPC support for platforms. This patch enables IPC only for BXT/KBL platform as for SKL recommendation is to keep is disabled. IPC (Isochronous Priority Control) is the hardware feature, which dynamically controles the memory read

[Intel-gfx] [PATCH v4 2/8] drm/i915/skl: New ddb allocation algorithm

From: Mahesh Kumar This patch implements new DDB allocation algorithm as per HW team recommendation. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of enabling

[Intel-gfx] [PATCH v4 4/8] drm/i915/gen9: WM memory bandwidth related workaround

-by: "Kumar, Mahesh" <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 9 +++ drivers/gpu/drm/i915/intel_drv.h | 11 +++ drivers/gpu/drm/i915/intel_pm.c | 146 +++ 3 files changed, 166 insertions(+) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH v4 6/8] drm/i915/skl: Add variables to check x_tile and y_tile

From: Mahesh Kumar This patch adds variable to check for X_tiled & y_tiled planes, instead of always checking against framebuffer-modifiers. Changes: - Created separate patch as per Paulo's comment - Added x_tiled variable as well Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v4 3/8] drm/i915: Decode system memory bandwidth

This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Changes from v1: - Address comments from Paulo - implement decode function for SKL/KBL also Signed-off-by: "Kumar, Mahesh" &

[Intel-gfx] [PATCH v4 5/8] drm/i915/skl+: reset y_plane ddb structure also during calculation

From: Mahesh Kumar Current code clears only plane ddb allocation if total ddb allocated to pipe in zero. y_plane ddb still contains old value, clear that as well. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 1 + 1 file

[Intel-gfx] [PATCH v4 7/8] drm/i915/skl+: change WM calc to fixed point 16.16

From: Mahesh Kumar This patch changes Watermak calculation to fixed point calculation. Problem with current calculation is during plane_blocks_per_line calculation we divide intermediate blocks with min_scanlines and takes floor of the result because of integer

Re: [Intel-gfx] [PATCH] drm/i915/skl+: ddb allocation algorithm optimization

On 5/22/2018 1:27 PM, Maarten Lankhorst wrote: Hey, Op 21-05-18 om 13:36 schreef Mahesh Kumar: From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> This patch implements new DDB allocation algorithm as per HW team recommendation. This algo takecare of scenario where we allocate

Re: [Intel-gfx] [PATCH 03/24] drm/i915/icl: introduce tc_port

Reviewed-by: Mahesh Kumar On 5/22/2018 5:55 AM, Paulo Zanoni wrote: Add and enum for TC ports and auxiliary functions to handle them. Icelake brings a lot of registers and other things that only apply to the TC ports and are indexed starting from 0, so having an enum

Re: [Intel-gfx] [PATCH 08/10] drm/i915/crc: implement get_crc_sources callback

Hi, thanks for review. On 6/26/2018 1:59 PM, Daniel Vetter wrote: On Tue, Jun 26, 2018 at 11:52:57AM +0530, Mahesh Kumar wrote: This patch implements get_crc_sources callback, which returns list of all the valid crc sources supported by driver in current platform. Signed-off-by: Mahesh Kumar

Re: [Intel-gfx] [PATCH 02/10] drm: crc: Introduce pre_crc_read function

Hi, On 6/27/2018 8:48 PM, Maarten Lankhorst wrote: Op 27-06-18 om 16:44 schreef Mahesh Kumar: This patch implements a callback function "pre_crc_read" which will be called before crc read. In this function driver can implement and preparation work required for successfully reading CRC data.

Re: [Intel-gfx] [PATCH 04/10] drm/rockchip/crc: Implement verify_crc_source callback

Hi, On 6/27/2018 5:30 PM, Jani Nikula wrote: On Tue, 26 Jun 2018, Mahesh Kumar wrote: This patch implements "verify_crc_source" callback function for rockchip drm driver. Signed-off-by: Mahesh Kumar Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 21

Re: [Intel-gfx] [PATCH 09/10] drm/crc: Cleanup crtc_crc_open function

Cc: Laurent Pinchart On 6/26/2018 11:52 AM, Mahesh Kumar wrote: This patch make changes to allocate crc-entries buffer before enabling CRC generation. It moves all the failure check early in the function before setting the source or memory allocation. Now set_crc_source takes only two

Re: [Intel-gfx] [PATCH 06/10] drm/rcar-du/crc: Implement verify_crc_source callback

Cc: Laurent Pinchart On 6/26/2018 11:52 AM, Mahesh Kumar wrote: This patch implements "verify_crc_source" callback function for rcar drm driver. Signed-off-by: Mahesh Kumar Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 40

Re: [Intel-gfx] [PATCH 00/10] Improve crc-core driver interface

Cc:dri-de...@lists.freedesktop.org On 6/26/2018 11:52 AM, Mahesh Kumar wrote: This series improves crc-core <-> driver interface. This series adds following functionality in the crc-core - Now control node will print all the available sources if implemented by driver along with current

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: expect setting bad source to fail

Hi, On 7/2/2018 4:57 PM, Maarten Lankhorst wrote: Op 02-07-18 om 13:16 schreef Mahesh Kumar: Now crc-core framework verifies the source string passed by the user. So setting bad-source will fail. Expect file write to fail in bad-source subtest of kms_pipe_crc_basic. Signed-off-by: Mahesh

Re: [Intel-gfx] [PATCH v2] drm/i915/skl+: ddb allocation algorithm optimization

Hi, On 7/3/2018 4:56 AM, Rodrigo Vivi wrote: On Fri, Jun 29, 2018 at 03:13:35PM +0530, Mahesh Kumar wrote: This patch implements new DDB allocation algorithm as per HW team recommendation. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate,

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Optimize use of DBuf slices (rev2)

Hi, On 4/26/2018 3:24 AM, Rodrigo Vivi wrote: On Wed, Apr 25, 2018 at 09:46:23PM -, Patchwork wrote: == Series Details == Series: Optimize use of DBuf slices (rev2) URL : https://patchwork.freedesktop.org/series/41180/ State : failure == Summary == Applying: drm/i915/icl: track dbuf

Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init

Hi, On 1/30/2018 9:35 AM, Srinivas, Vidya wrote: -Original Message- From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] Sent: Monday, January 29, 2018 10:47 PM To: Srinivas, Vidya ; intel- g...@lists.freedesktop.org Subject: Re: [Intel-gfx]

Re: [Intel-gfx] [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

Hi, On 2/2/2018 6:26 PM, Jani Nikula wrote: On Fri, 02 Feb 2018, Mahesh Kumar wrote: Platforms before Gen11 were sharing lanes between port-A & port-E. This limitation is no more there. Changes since V1: - optimize the code (Shashank/Jani) - create helper

Re: [Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

Hi, On 2/8/2018 2:01 PM, Sharma, Shashank wrote: Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last

Re: [Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

Hi, On 2/7/2018 10:12 PM, Sharma, Shashank wrote: Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register

Hi, Reviewed-by: Mahesh Kumar -Mahesh On 8/1/2018 6:16 AM, Paulo Zanoni wrote: We don't have proper watermark NV12 support on ICL due to differences in how it should be implemented. In commit 234059da0f33 ("drm/i915/icl: NV12 y-plane ddb is not in same plane") we avoided writi

Re: [Intel-gfx] [PATCH] drm/i915/skl: distribute DDB based on panel resolution

Hi Chris, Thanks for review. On 7/30/2018 9:08 PM, Chris Wilson wrote: Quoting Mahesh Kumar (2018-07-30 15:12:02) We distribute DDB equally among all pipes irrespective of display buffer requirement of each pipe. This leads to a situation where high resolution y-tiled display can not be

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers are fixed in Bspec I don't know if this form is common in the kernel, but in Mesa we specify the name of the page

Re: [Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

Hi, Patch LGTM. Reviewed-by: Mahesh Kumar thanks, -Mahesh On 6/8/2018 4:37 AM, Paulo Zanoni wrote: While things may have been different before, right now the function is very simple and has a single caller. IMHO any possible benefits from an abstraction here are gone and not worth the price

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

Hi, On 7/28/2018 11:18 AM, Rodrigo Vivi wrote: On Fri, Jul 27, 2018 at 11:40:14AM +0530, Kumar, Mahesh wrote: Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_pipe_crc_basic: expect setting bad source to fail

Hi, On 8/2/2018 4:13 PM, Maarten Lankhorst wrote: Op 02-08-18 om 12:42 schreef Maarten Lankhorst: Op 02-07-18 om 13:27 schreef Maarten Lankhorst: Op 02-07-18 om 13:16 schreef Mahesh Kumar: Now crc-core framework verifies the source string passed by the user. So setting bad-source will fail.

Re: [Intel-gfx] [PATCH 1/5] drm/i915/bxt: Decode memory bandwidth and parameters

Hi, On 8/17/2018 11:13 PM, Rodrigo Vivi wrote: On Thu, Jul 26, 2018 at 07:44:06PM +0530, Mahesh Kumar wrote: This patch adds support to decode system memory bandwidth and other parameters for broxton platform, which will be used for arbitrated display memory bandwidth calculation in GEN9

Re: [Intel-gfx] [PATCH V2 1/3] drm/vkms/crc: Implement verify_crc_source callback

Hi Haneen, On 8/21/2018 4:09 AM, Haneen Mohammed wrote: On Tue, Aug 14, 2018 at 08:31:03AM +0530, Mahesh Kumar wrote: This patch implements "verify_crc_source" callback function for Virtual KMS drm driver. Changes Since V1: - update values_cnt in verify_crc_source Cc: Haneen Mohammed

Re: [Intel-gfx] [PATCH 2/5] drm/i915/skl+: Decode memory bandwidth and parameters

Hi, On 8/17/2018 4:05 AM, Rodrigo Vivi wrote: On Thu, Jul 26, 2018 at 07:44:07PM +0530, Mahesh Kumar wrote: This patch adds support to decode system memory bandwidth and other parameters for skylake and Gen9+ platforms, which will be used for arbitrated display memory bandwidth calculation in

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions

Hi, Please include platform name in subject line: On 8/27/2018 12:17 PM, Swati Sharma wrote: From: Vidya Srinivas Added needed plane control flag definitions for Y210, Y212 and Y216 formats. may be, add more info in commit message -Mahesh Signed-off-by: Swati Sharma Signed-off-by:

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats

Hi, On 8/27/2018 12:17 PM, Swati Sharma wrote: From: Vidya Srinivas Signed-off-by: Swati Sharma Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 15 +++ drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 2 files changed, 18 insertions(+) diff --git

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes

On 8/27/2018 12:17 PM, Swati Sharma wrote: From: Vidya Srinivas In this patch, a list for icl specific pixel formats is created in which Y210, Y212 and Y216 pixel formats are added along with legacy pixel formats for primary and sprite plane. Signed-off-by: Swati Sharma Signed-off-by:

Re: [Intel-gfx] [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc

On 8/27/2018 12:47 PM, Kumar, Mahesh wrote: Hi, On 8/27/2018 12:17 PM, Swati Sharma wrote: From: Vidya Srinivas The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies

Re: [Intel-gfx] [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc

Hi, On 8/27/2018 12:17 PM, Swati Sharma wrote: From: Vidya Srinivas The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies a DWORD. Y210: Valid data occupies MSB 10 bits.

Re: [Intel-gfx] [PATCH 4/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

Hi, On 8/22/2018 12:26 AM, Rodrigo Vivi wrote: On Tue, Aug 21, 2018 at 09:30:21PM +0530, Kumar, Mahesh wrote: Hi, On 8/21/2018 8:27 PM, Kumar, Mahesh wrote: Hi, On 8/17/2018 11:50 PM, Rodrigo Vivi wrote: On Thu, Jul 26, 2018 at 07:44:09PM +0530, Mahesh Kumar wrote: IPC may cause

Re: [Intel-gfx] [PATCH 4/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

Hi, On 8/21/2018 8:27 PM, Kumar, Mahesh wrote: Hi, On 8/17/2018 11:50 PM, Rodrigo Vivi wrote: On Thu, Jul 26, 2018 at 07:44:09PM +0530, Mahesh Kumar wrote: IPC may cause underflows if not used with dual channel symmetric memory configuration. Disable IPC for non symmetric configurations

Re: [Intel-gfx] [PATCH 4/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

Hi, On 8/17/2018 11:50 PM, Rodrigo Vivi wrote: On Thu, Jul 26, 2018 at 07:44:09PM +0530, Mahesh Kumar wrote: IPC may cause underflows if not used with dual channel symmetric memory configuration. Disable IPC for non symmetric configurations in affected platforms. Display WA #1141

Re: [Intel-gfx] [PATCH v4 10/10] drm/rcar-du/crc: Implement get_crc_sources callback

Hi Laurent! Thanks for the review. :) will update patch and resubmit -Mahesh On 7/19/2018 4:42 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patch. On Friday, 13 July 2018 16:59:42 EEST Mahesh Kumar wrote: This patch implements get_crc_sources callback, which returns list of

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement 16GB dimm wa for latency level-0

Hi, Thanks for review. On 7/13/2018 8:27 PM, Ville Syrjälä wrote: On Fri, Jul 13, 2018 at 07:41:24PM +0530, Mahesh Kumar wrote: Memory with 16GB dimms require an increase of 1us in level-0 latency. This patch implements the same. Bspec: 4381 Signed-off-by: Mahesh Kumar ---

Re: [Intel-gfx] [PATCH 0/3] Decode memdev info and bandwidth and implemnt latency WA

On 7/13/2018 8:21 PM, Ville Syrjälä wrote: On Fri, Jul 13, 2018 at 07:41:21PM +0530, Mahesh Kumar wrote: This series adds support to calculate system memdev parameters and calculate What's "memdev"? memory device. -Mahesh total system memory bandwidth. This parameters and BW will be used

Re: [Intel-gfx] [PATCH 00/10] Improve crc-core driver interface

Hi, thanks for the review. On 7/12/2018 4:38 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patches. When resubmitting patch series, could you please add a version number to the [PATCH] prefix ? Otherwise it gets difficult to figure out which version is the latest. This can be

Re: [Intel-gfx] [PATCH 0/3] Decode memdev info and bandwidth and implemnt latency WA

Hi, On 7/18/2018 5:33 PM, Ville Syrjälä wrote: On Sat, Jul 14, 2018 at 07:42:17PM +0530, Kumar, Mahesh wrote: On 7/13/2018 8:21 PM, Ville Syrjälä wrote: On Fri, Jul 13, 2018 at 07:41:21PM +0530, Mahesh Kumar wrote: This series adds support to calculate system memdev parameters

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement 16GB dimm wa for latency level-0

Hi, On 7/18/2018 5:34 PM, Ville Syrjälä wrote: On Sat, Jul 14, 2018 at 07:40:43PM +0530, Kumar, Mahesh wrote: Hi, Thanks for review. On 7/13/2018 8:27 PM, Ville Syrjälä wrote: On Fri, Jul 13, 2018 at 07:41:24PM +0530, Mahesh Kumar wrote: Memory with 16GB dimms require an increase of 1us

Re: [Intel-gfx] [PATCH v2] drm/i915: use for_each_pipe loop to assign crtc_mask

Hi, I used u8 because internally num_pipes variable used by for_each_pipe macro is of u8 type. If you think it's good to have int for consistency I can update the patch. Regards, -Mahesh On 9/7/2018 6:34 PM, Jani Nikula wrote: On Fri, 07 Sep 2018, Mahesh Kumar wrote: This cleanup patch

Re: [Intel-gfx] [PATCH 01/10] drm: crc: Introduce verify_crc_source callback

Hi, Thanks for the review, On 7/10/2018 4:56 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patch. On Monday, 2 July 2018 14:07:20 EEST Mahesh Kumar wrote: This patch adds a new callback function "verify_crc_source" which will be used during setting the crc source in control node

Re: [Intel-gfx] [PATCH 02/10] drm: crc: Introduce get_crc_sources callback

Hi, thanks for the review. On 7/10/2018 4:52 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patch. On Monday, 2 July 2018 14:07:21 EEST Mahesh Kumar wrote: This patch introduce a callback function "get_crc_sources" which will be called during read of control node. It is an optional

Re: [Intel-gfx] [PATCH 02/10] drm: crc: Introduce get_crc_sources callback

Hi, On 7/10/2018 5:39 PM, Laurent Pinchart wrote: Hi Mahesh, On Tuesday, 10 July 2018 15:01:38 EEST Kumar, Mahesh wrote: On 7/10/2018 4:52 PM, Laurent Pinchart wrote: Hi Mahesh, On Monday, 2 July 2018 14:07:21 EEST Mahesh Kumar wrote: This patch introduce a callback function

Re: [Intel-gfx] [PATCH 01/10] drm: crc: Introduce verify_crc_source callback

Hi, On 7/10/2018 5:40 PM, Laurent Pinchart wrote: Hi Mahesh, On Tuesday, 10 July 2018 14:54:11 EEST Kumar, Mahesh wrote: On 7/10/2018 4:56 PM, Laurent Pinchart wrote: On Monday, 2 July 2018 14:07:20 EEST Mahesh Kumar wrote: This patch adds a new callback function "verify_crc_source&q

Re: [Intel-gfx] [PATCH 05/10] drm/rcar-du/crc: Implement verify_crc_source callback

Hi, thanks foe the review. On 7/10/2018 5:07 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patch. On Monday, 2 July 2018 14:07:24 EEST Mahesh Kumar wrote: This patch implements "verify_crc_source" callback function for rcar drm driver. Signed-off-by: Mahesh Kumar Cc:

Re: [Intel-gfx] [PATCH 08/10] drm/crc: Cleanup crtc_crc_open function

Hi, Thanks for the review. On 7/10/2018 5:19 PM, Laurent Pinchart wrote: Hi Mahesh, Thank you for the patch. On Monday, 2 July 2018 14:07:27 EEST Mahesh Kumar wrote: This patch make changes to allocate crc-entries buffer before enabling CRC generation. It moves all the failure check early

Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register

Hi, On 3/10/2018 2:21 AM, Lucas De Marchi wrote: On Fri, Mar 09, 2018 at 11:55:47AM -0800, Rodrigo Vivi wrote: On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote: This patch creates a new macro to get PORT_TX register for any given DW. This will remove the need of defining register

Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: track dbuf slice-2 status

Hi, On 4/5/2018 1:55 PM, Jani Nikula wrote: On Thu, 05 Apr 2018, Mahesh Kumar wrote: This patch adds support to start tracking status of DBUF slices. This is foundation to introduce support for enabling/disabling second DBUF slice dynamically for ICL. Signed-off-by:

Re: [Intel-gfx] [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation.

Please review. thanks, -Mahesh On 2/6/2018 11:38 AM, Mahesh Kumar wrote: Platforms before Gen11 were sharing lanes between port-A & port-E. This limitation is no more there. Changes since V1: - optimize the code (Shashank/Jani) - create helper function to get max lanes (ville) Changes

Re: [Intel-gfx] [PATCH] drm/i915/icl: MBUS B credit change

Hi, LGTM Reviewed-by: Mahesh Kumar On 10/4/2018 8:48 PM, Rodrigo Vivi wrote: No functional change. But just a minor change to keep up with Spec, since it has changed since commit c3cc39c539d4 ("drm/i915/icl: program mbus during pipe enable") The instructions previously said to program

Re: [Intel-gfx] [PATCH v4] drm/i915: use for_each_pipe loop to assign crtc_mask

Hi, just a ping for review :) -Mahesh On 9/8/2018 11:40 AM, Mahesh Kumar wrote: This cleanup patch makes changes to use for_each_pipe loop during bit-mask assignment of allowed crtc with encoder. changes: - use BIT(i) macro instead of (1 << i) (Chris) changes from V2: - use int for

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