On Mon, May 13, 2019 at 12:45:52PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself
Chris Wilson
Cc: Michal Wajdeczko
---
Reviewed-by: Matthew Brost
drivers/gpu/drm/i915/intel_guc_ct.c | 15 +++
drivers/gpu/drm/i915/intel_guc_ct.h | 4
drivers/gpu/drm/i915/intel_uc.c | 19 ---
3 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drive
lson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 13 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/
paths can be considered dead and removed.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++---
drivers/gpu
of '1'). Other values flush
the log relay as before.
v2: Style changes and fix typos. Add guc_log_relay_stop()
function. (Daniele)
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 53
we can safely drop it.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 22 +++--
drivers/gpu/drm/i915/gt/intel_lrc.h| 23 ++
drivers/gpu
again, just disable the command for now and add a note
that we'll implement it as part of the new flow.
[1] https://patchwork.freedesktop.org/patch/295038/
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Cc: Fernando Pacheco
---
drivers/gpu/drm
On Thu, Nov 21, 2019 at 12:58:50PM +0100, Michal Wajdeczko wrote:
On Thu, 21 Nov 2019 00:56:03 +0100, wrote:
From: Matthew Brost
CTB writes are now in the path of command submission and should be
optimized for performance. Rather than reading CTB descriptor values
(e.g. head, tail, size
On Thu, Nov 21, 2019 at 01:25:05PM +0100, Michal Wajdeczko wrote:
On Thu, 21 Nov 2019 00:56:04 +0100, wrote:
From: Matthew Brost
With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits
On Thu, Nov 21, 2019 at 12:43:26PM +0100, Michal Wajdeczko wrote:
On Thu, 21 Nov 2019 00:56:02 +0100, wrote:
From: Matthew Brost
Add non blocking CTB send fuction, intel_guc_send_nb. In order to
support a non blocking CTB send fuction a spin lock is needed to
2x typos
protect the CTB
On Thu, Nov 21, 2019 at 04:13:25PM -0800, Matthew Brost wrote:
On Thu, Nov 21, 2019 at 12:43:26PM +0100, Michal Wajdeczko wrote:
On Thu, 21 Nov 2019 00:56:02 +0100, wrote:
From: Matthew Brost
Add non blocking CTB send fuction, intel_guc_send_nb. In order to
support a non blocking CTB send
On Thu, Nov 21, 2019 at 07:56:07AM -0800, Matthew Brost wrote:
On Thu, Nov 21, 2019 at 12:58:50PM +0100, Michal Wajdeczko wrote:
On Thu, 21 Nov 2019 00:56:03 +0100, wrote:
From: Matthew Brost
CTB writes are now in the path of command submission and should be
optimized for performance
On Wed, Dec 11, 2019 at 01:34:20PM -0800, Daniele Ceraolo Spurio wrote:
On 12/11/19 1:22 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:42)
Having the virtual engine handling in its own file will make it easier
call it from or modify for the GuC implementation
: Tvrtko Ursulin
Cc: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 154 ++---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12 +-
2 files changed, 93 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.
On Wed, Sep 25, 2019 at 10:59:32AM -0700, Daniele Ceraolo Spurio wrote:
+ Matt
I've reviewed this patch and this affects some of the work I'm doing on the new
GuC interface. For the new GuC interface I have two patches that rework the HW
ID assignment.
The first patch moves ownership of the
On Fri, Jan 31, 2020 at 03:33:55PM +, Chris Wilson wrote:
Quoting Michal Wajdeczko (2020-01-31 14:58:34)
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive" buffer to send
back response messages, since almost all returned
.org/series/72031/
[2] https://patchwork.freedesktop.org/series/70787/
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Daniele Ceraolo Spurio (6):
drm/i915/guc: Add guc-specific breadcrumb functions
drm/i915/guc: Add request_alloc for guc_submission
drm/i915/guc:
On Thu, Jan 07, 2021 at 04:45:31PM +, Chris Wilson wrote:
> Quoting Matthew Brost (2021-01-07 16:05:07)
> > On Tue, Dec 29, 2020 at 12:01:25PM +, Chris Wilson wrote:
> > > The first "scheduler" was a topographical sorting of requests into
> > >
On Thu, Dec 17, 2020 at 09:15:24AM +, Chris Wilson wrote:
> Matthew Brost pointed out that the while-loop on a shared breadcrumb was
> inherently fraught with danger as it competed with the other users of
> the breadcrumbs. However, in order to completely drain the re-arming irq
;
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/i915_sw_fence.c | 25 +++--
> 1 file changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
> b/drivers/gpu/drm/i915/
*/
> + ktime_t start;
> + } stats;
> +
> struct intel_engine_cs *engine[I915_NUM_ENGINES];
> struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
> [MAX_ENGINE_INSTANCE + 1];
> diff --git a
On Thu, Dec 10, 2020 at 08:02:20AM +, Chris Wilson wrote:
> When we reset the legacy ring context, due to potential corruption over
> suspend/resume, remove the valid bit so that we avoid loading garbage.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
> ---
>
epped out
> of the lists.
>
> Signed-off-by: Chris Wilson
Makes sense to me.
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 +++--
> drivers/gpu/drm/i915/gt/intel_lrc.c | 15 +++
> 2 files changed, 18 insertions(+), 2 d
On Thu, Dec 10, 2020 at 08:02:37AM +, Chris Wilson wrote:
> Explicitly differentiate between the absolute and relative timelines,
> and the global HWSP and ppHWSP relative offsets. When using a timeline
> that is relative to a known status page, we can replace the absolute
> addressing in the
while (atomic_read(>breadcrumbs->signaler_active))
> + cpu_relax();
Would a 'cond_resched' be better here? I trust your opinion on which to
use but thought I'd mention it.
With that:
Reviewed-by: Matthew Brost
> }
>
> if (RE
t; and so we can then reset all seqno values by walking that list.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 -
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6
> drivers/gpu/drm/i915
935ed5339c4
> ("drm/i915: Remove logical HW ID"). As we can now free the GEM context
> immediately from any context, remove the deferral of the free_list
>
> v2: Lift removing the context from the global list into close().
>
> Suggested-by: Mika Kuoppala
> Signed-off-by
On Thu, Dec 10, 2020 at 08:02:38AM +, Chris Wilson wrote:
> Relative timelines are relative to either the global or per-process
> HWSP, and so we can replace the absolute addressing with store-index
> variants for position invariance.
>
Can you explain the benifit of relative addressing? Why
relocate them.
>
Reviewed-by: Matthew Brost
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 37 +++
> 1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/g
On Thu, Dec 10, 2020 at 09:00:53PM +, Chris Wilson wrote:
> Quoting Matthew Brost (2020-12-10 19:28:06)
> > On Thu, Dec 10, 2020 at 08:02:37AM +, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > b/drivers/gpu/drm/i91
the context state, we may not necessarily use a position
> within the first page and so need more than 12b.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen8_engine_cs.
On Thu, Dec 10, 2020 at 09:05:44PM +, Chris Wilson wrote:
> Quoting Matthew Brost (2020-12-10 19:16:44)
> > On Thu, Dec 10, 2020 at 08:02:38AM +, Chris Wilson wrote:
> > > Relative timelines are relative to either the global or per-process
> > > HWSP, and so
On Fri, Oct 16, 2020 at 12:43:45PM +0200, Maarten Lankhorst wrote:
> i915_vma_pin may fail with -EDEADLK when we start locking page tables,
> so ensure we handle this correctly.
>
> Signed-off-by: Maarten Lankhorst
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 23 +++
>
> the CTB registration, so there is still no need to explicitly do so.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/2469
> Signed-off-by: Daniele Ceraolo Spurio
Looks good to me.
Reviewed-by: Matthew Brost
> Cc: Michal Wajdeczko
> Cc: Matthew
On Tue, Dec 29, 2020 at 12:01:25PM +, Chris Wilson wrote:
> The first "scheduler" was a topographical sorting of requests into
> priority order. The execution order was deterministic, the earliest
> submitted, highest priority request would be executed first. Priority
> inheritance ensured
On Mon, Jan 25, 2021 at 02:01:15PM +, Chris Wilson wrote:
> Replace the priolist rbtree with a skiplist. The crucial difference is
> that walking and removing the first element of a skiplist is O(1), but
> O(lgN) for an rbtree, as we need to rebalance on remove. This is a
> hindrance for
On Thu, Jun 10, 2021 at 03:35:57PM +0200, Michal Wajdeczko wrote:
>
>
> On 10.06.2021 06:36, Matthew Brost wrote:
> > As part of enabling GuC submission [1] we need to update to the latest
> > and greatest firmware. This series does that. This is a destructive
> &g
On Thu, Jun 10, 2021 at 03:19:50PM +0200, Michal Wajdeczko wrote:
>
>
> On 10.06.2021 06:38, Matthew Brost wrote:
> > On Wed, Jun 09, 2021 at 10:07:21PM +0200, Michal Wajdeczko wrote:
> >>
> >>
> >> On 09.06.2021 19:36, John Harrison wrote:
> >&g
On Mon, Jun 07, 2021 at 03:19:11PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 6/7/2021 11:03 AM, Matthew Brost wrote:
> > As part of enabling GuC submission [1] we need to update to the latest
> > and greatest firmware. This series does that. This is a destructive
> &g
Move active request tracking and its lock to i915_sched_engine. This
lock is also the submission lock so having it in the i915_sched_engine
is the correct place.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt
Rather passing around an intel_engine_cs in the scheduling code, pass
around a i915_sched_engine.
v3:
(Jason Ekstrand)
Add READ_ONCE around rq->engine in lock_sched_engine
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
.../drm/i915/gt/intel_execlists_submission.c |
object.
v3:
(Jason Ekstrand)
Update comment next to intel_engine_cs.virtual
Add kernel doc
(Checkpatch)
Fix double the in commit message
v4:
(Daniele)
Update comment message.
Add comment about subclass field
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Add wrapper function around RB tree to determine if i915_sched_engine is
empty.
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++---
drivers/gpu/drm/i915/gt/uc
Not all back-ends require a kick after a scheduling update, so make the
kick a call-back function that the back-end can opt-in to. Also move
the current kick function from the scheduler to the execlists file as it
is specific to that back-end.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele
(Matthew Brost):
- Drop wrapper functions for tasklet as eventually tasklet will be
dropped
v3:
(Jason Ekstrand)
- Address his comments, change logs in individual patches
- Squash documentation patch into previous patches as needed
(Checkpatch)
- Fix warnings
(Docs)
- Fix warnings
The schedule function should be in the schedule object.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 ---
drivers
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 2 --
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 ++
drivers/gpu/drm/i915/i915_scheduler.h| 7
(CI)
Rebase and fix build error
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 --
.../drm/i915/gt/intel_execlists_submission.c |
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Daniele Ceraolo
From: Michal Wajdeczko
Most of the changes to the 62.0.0 firmware revolved around CTB
communication channel. Conform to the new (stable) CTB protocol.
Signed-off-by: John Harrison
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
: Address comments, looking for remaning RBs so patches can be
squashed and sent for CI
v3: Delete a few unused defines, squash patches
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/89844
[2] https://patchwork.freedesktop.org/series/91341
Michal Wajdeczko (3):
drm/i915
From: Michal Wajdeczko
GuC ABI documentation is now ready to be included in i915.rst
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski
Reviewed-by: Matthew Brost
---
Documentation/gpu/i915.rst | 8
1 file changed, 8 insertions(+)
diff --git
From: Michal Wajdeczko
GuC ABI documentation is now ready to be included in i915.rst
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski
Reviewed-by: Matthew Brost
---
Documentation/gpu/i915.rst | 8
1 file changed, 8 insertions(+)
diff --git
-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 107 ++
.../gt/uc/abi/guc_communication_ctb_abi.h | 126 +--
.../gt/uc/abi/guc_communication_mmio_abi.h| 65 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 107
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Daniele Ceraolo
: Address comments, looking for remaning RBs so patches can be
squashed and sent for CI
v3: Delete a few unused defines, squash patches
v4: Add values back into kernel doc, fix docs warning
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/89844
[2] https
off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 --
.../drm/i915/gt/intel_execlists_submission.c | 84 ++-
drivers/gpu/drm/i915/gt/mock_engin
object.
v3:
(Jason Ekstrand)
Update comment next to intel_engine_cs.virtual
Add kernel doc
(Checkpatch)
Fix double the in commit message
v4:
(Daniele)
Update comment message.
Add comment about subclass field
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
The schedule function should be in the schedule object.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 ---
drivers
Rather passing around an intel_engine_cs in the scheduling code, pass
around a i915_sched_engine.
v3:
(Jason Ekstrand)
Add READ_ONCE around rq->engine in lock_sched_engine
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
.../drm/i915/gt/intel_execlists_submission.c |
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 2 --
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 ++
drivers/gpu/drm/i915/i915_scheduler.h| 7
Move active request tracking and its lock to i915_sched_engine. This
lock is also the submission lock so having it in the i915_sched_engine
is the correct place.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt
Not all back-ends require a kick after a scheduling update, so make the
kick a call-back function that the back-end can opt-in to. Also move
the current kick function from the scheduler to the execlists file as it
is specific to that back-end.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele
Add wrapper function around RB tree to determine if i915_sched_engine is
empty.
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++---
drivers/gpu/drm/i915/gt/uc
(Matthew Brost):
- Drop wrapper functions for tasklet as eventually tasklet will be
dropped
v3:
(Jason Ekstrand)
- Address his comments, change logs in individual patches
- Squash documentation patch into previous patches as needed
(Checkpatch)
- Fix warnings
(Docs)
- Fix warnings
N_KB] = "RAMBO L3 bank size (in
> KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + uint32_t *data;
> + int i = 0;
> + int
m_i915_query_item query = {
> + .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
> + };
I believe you could just one of the local variables, right? I see the
comparison for 'query.length == size.length' but you store the length a
u32 rather than a struct.
Just a suggestion
On Mon, Jun 14, 2021 at 06:05:19PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 6/8/2021 12:17 PM, Matthew Brost wrote:
> > The submission tasklet operates on i915_sched_engine, thus it is the
> > correct place for it.
> >
> > v3:
> > (Jason Ekstr
direction.
This patch starts the aforementioned transition by moving the priolist
into the i915_sched_engine object.
v3:
(Jason Ekstrand)
Update comment next to intel_engine_cs.virtual
Add kernel doc
(Checkpatch)
Fix double the in commit message
Signed-off-by: Matthew Brost
(Matthew Brost):
- Drop wrapper functions for tasklet as eventually tasklet will be
dropped
v3:
(Jason Ekstrand)
- Address his comments, change logs in individual patches
- Squash documentation patch into previous patches as needed
(Checkpatch)
- Fix warnings
(Docs)
- Fix warnings
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 2 --
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 ++
drivers/gpu/drm/i915/i915_scheduler.h| 7
Rather than touching execlist specific structures in the generic
scheduling code, add a callback function in the backend.
Signed-off-by: Matthew Brost
---
.../drm/i915/gt/intel_execlists_submission.c | 52
drivers/gpu/drm/i915/i915_scheduler.c | 62
The submission tasklet operates on i915_sched_engine, thus it is the
correct place for it.
v3:
(Jason Ekstrand)
Change sched_engine->engine to a void* private data pointer
Add kernel doc
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14 ---
drivers/
Rather passing around an intel_engine_cs in the scheduling code, pass
around a i915_sched_engine.
v3:
(Jason Ekstrand)
Add READ_ONCE around rq->engine in lock_sched_engine
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
.../drm/i915/gt/intel_execlists_submission.c |
Add wrapper function around RB tree to determine if i915_sched_engine is
empty.
Signed-off-by: Matthew Brost
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++---
drivers/gpu/drm/i915/gt/uc
The schedule function should be in the schedule object.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 ---
drivers/gpu/drm/i915/gt
Move active request tracking and its lock to i915_sched_engine. This
lock is also the submission lock so having it in the i915_sched_engine
is the correct place.
v3:
(Jason Ekstrand)
Add kernel doc
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 2
On Thu, May 27, 2021 at 04:11:50PM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/2021 15:35, Matthew Brost wrote:
> > On Thu, May 27, 2021 at 11:02:24AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 26/05/2021 19:10, Matthew Brost wrote:
> > >
> >
On Mon, Jun 07, 2021 at 11:03:55AM -0700, Matthew Brost wrote:
> From: John Harrison
>
> Signed-off-by: John Harrison
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/
On Mon, Jun 07, 2021 at 09:38:58PM +0200, Michal Wajdeczko wrote:
>
>
> On 07.06.2021 19:45, Matthew Brost wrote:
> > On Mon, Jun 07, 2021 at 11:03:51AM -0700, Matthew Brost wrote:
> >> From: Michal Wajdeczko
> >>
> >> GuC ABI documentati
On Mon, Jun 07, 2021 at 11:03:52AM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> CTB pool is now maintained internally by the GuC as part of its
> "private data". No need to allocate separate buffer and pass it
> to GuC as yet another ADS.
>
> Si
From: Michal Wajdeczko
Once CTB descriptor is found in error state, either set by GuC
or us, there is no need continue checking descriptor any more,
we can rely on our internal flag.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Piotr Piórkowski
Reviewed-by: Matthew Brost
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Michał Winiarski
---
.../gpu/drm/i915/gt/uc
From: Michal Wajdeczko
The MMIO based Host-to-GuC communication protocol has been
updated to use unified HXG messages.
Update our intel_guc_send_mmio() function by correctly handle
BUSY, RETRY and FAILURE replies. Also update our documentation.
GuC: 55.0.0
Signed-off-by: Matthew Brost
Signed
From: Michal Wajdeczko
Format of the STATUS dword in CTB response message now follows
definition of the HXG header. Update our code and remove any
obsolete legacy definitions.
GuC: 55.0.0
Signed-off-by: Michal Wajdeczko
Acked-by: Piotr Piórkowski
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
From: John Harrison
GuC firmware v53.0.0 introduced per context scheduling policies. This
includes changes to some of the ADS structures which are required to
load the firmware even if not using GuC submission.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew
On Mon, Jun 07, 2021 at 11:03:54AM -0700, Matthew Brost wrote:
> From: John Harrison
>
> GuC v57 unified the 'DPC' and 'ISR' buffers into a single buffer with
> the option for it to be larger.
>
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> Signed-off-by
On Mon, Jun 07, 2021 at 11:03:51AM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> GuC ABI documentation is now ready to be included in i915.rst
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> Cc: Piotr Piórkowski
Michal - I noticed whil
From: Michal Wajdeczko
New GuC does not require it any more.
Reviewed-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Piotr Piórkowski
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 8 +---
2 files changed, 1 insertion
From: Michal Wajdeczko
CTB pool is now maintained internally by the GuC as part of its
"private data". No need to allocate separate buffer and pass it
to GuC as yet another ADS.
Signed-off-by: Matthew Brost #v4
Signed-off-by: Michal Wajdeczko
Cc: Janusz Krzysztofik
---
drivers/gp
From: Michal Wajdeczko
Definition of the CTB descriptor has changed, leaving only
minimal shared fields like HEAD/TAIL/STATUS.
Both HEAD and TAIL are now in dwords.
Add some ABI documentation and implement required changes.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
From: Michal Wajdeczko
Definition of the CTB registration action has changed.
Add some ABI documentation and implement required changes.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski #4
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 107
From: Michal Wajdeczko
Format of the CTB messages has changed:
- support for multiple formats
- message fence is now part of the header
- reuse of unified HXG message formats
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski
---
.../gt/uc/abi
into a single patch for merging.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/89844/
John Harrison (3):
drm/i915/guc: Support per context scheduling policies
drm/i915/guc: Unified GuC log
drm/i915/guc: Update firmware to v62.0.0
Michal Wajdeczko (10):
drm/i915/guc
From: John Harrison
GuC v57 unified the 'DPC' and 'ISR' buffers into a single buffer with
the option for it to be larger.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 15 ---
drivers/gpu/drm/i915/gt/uc
From: John Harrison
Signed-off-by: John Harrison
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 26
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
From: Michal Wajdeczko
GuC ABI documentation is now ready to be included in i915.rst
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski
---
Documentation/gpu/i915.rst | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/gpu/i915.rst b
From: Michal Wajdeczko
Once CTB descriptor is found in error state, either set by GuC
or us, there is no need continue checking descriptor any more,
we can rely on our internal flag.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Piotr Piórkowski
---
drivers/gpu/drm/i915
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc: Michał Winiarski
---
.../gpu/drm/i915/gt/uc
From: Michal Wajdeczko
Format of the CTB messages has changed:
- support for multiple formats
- message fence is now part of the header
- reuse of unified HXG message formats
v2:
(Daniele)
- Better comment in ct_write()
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc
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