num intel_dpll_id id)
> +static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
> {
> - return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> + return id - DPLL_ID_ICL_MGPLL1;
> }
>
> -enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
> +enum intel_dpll_
state->shared_dpll;
> @@ -1004,10 +1004,11 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct
> intel_encoder *encoder,
>
> switch (id) {
> default:
> + /*
> + * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be use
s
Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> Instead of looping again on the range of plls, just keep track of one
> unused one and use it later.
>
Reviewed-by: Paulo Zanoni
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/int
Em qui, 2019-01-24 às 10:52 -0800, Lucas De Marchi escreveu:
> On Wed, Jan 23, 2019 at 05:15:26PM -0800, Paulo Zanoni wrote:
> > Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> > > Fix the TODO leftover in the code by changing the argument in MG_PLL
> > >
r DPLL0
> when the latter was most definitely available).
Reviewed-by: Paulo Zanoni
>
> Cc: Lucas De Marchi
> Cc: Paulo Zanoni
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> d
Em qui, 2019-05-02 às 11:29 +0300, Jani Nikula escreveu:
> Using arithmetic operators with booleans is confusing. Switch to logical
> operators.
>
> Cc: Paulo Zanoni
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1
file?
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/
gned-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 125 +-
> 1 file changed, 73 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c
> b/drivers/gpu
> Total: Before=1544400, After=1544366, chg -0.00%
>
> Win some, lose some, gcc is gcc.
>
> Signed-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 122
em in the macro callers. Doing that
should be very simple now.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 100
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
niele Ceraolo Spurio
Paulo Zanoni (3):
drm/i915: refactor the IRQ init/reset macros
drm/i915: convert the IRQ initialization functions to intel_uncore
drm/i915: fully convert the IRQ initialization macros to intel_uncore
drivers/gpu/drm/i915/i915_irq.c | 275 +++-
1
_irq_reset 1100 333-767
gen11_irq_reset 1959 686 -1273
Total: Before=2262051, After=2256428, chg -0.25%
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 123 +++-
1 file changed, 73 inserti
Make them take the uncore argument from the caller instead of passing
the implicit &dev_priv->uncore directly. This will allow us to finally
pass something that's not dev_priv->uncore in the future, and gets rid
of the implicit variables in register macros.
Signed-off-b
Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore
> URL : https://patchwork.freedesktop.org/series/59202/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 7f73d1fe31bb drm/i915:
Em ter, 2019-04-09 às 21:10 +0300, Ville Syrjälä escreveu:
> On Mon, Apr 08, 2019 at 05:37:27PM -0700, Paulo Zanoni wrote:
> > The whole point of having macros here is for the token pasting
> > necessary to automatically have IMR, IIR and IER selected. We don't
> > r
Em ter, 2019-04-09 às 21:20 +0300, Ville Syrjälä escreveu:
> On Tue, Apr 09, 2019 at 10:34:22AM -0700, Paulo Zanoni wrote:
> > Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloa
in v2:
- Two additional patches based on the discussion with Ville and Checkpatch.
- No more checkpatch complaints.
Cc: Ville Syrjälä
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Paulo Zanoni (5):
drm/i915: refactor the IRQ init/reset macros
drm/i915: don't specify the IRQ register i
tead of passing them through variables.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++--
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 60a3f4203ac3..b1f1
e newer patches.
Reviewed-by: Ville Syrjälä (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 144 +++-
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
ind
have so many instances of IIR/IMR in comments that
adding a prefix would make the users of these register more easily
findable, in addition to make our token pasting macros actually
readable. So IMHO opening an exception here is worth it.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
em in the macro callers. Doing that
should be very simple now.
v2: Rebase on top of the new patches.
Reviewed-by: Ville Syrjälä (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 97 -
1 file changed, 48 insertions(+), 49 deletions(-)
diff --
rjälä (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 136
1 file changed, 86 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8d8935d71180..60a3f4203ac3 100644
--- a/drivers/gp
Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore (rev2)
> URL : https://patchwork.freedesktop.org/series/59202/
> State : success
So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
ema
Em seg, 2019-04-15 às 09:42 +0300, Tomi Sarvela escreveu:
> On 4/12/19 11:57 PM, Paulo Zanoni wrote:
> > Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloat and conversion
niLake until a solution is found.
> >
> > Buglink: https://bugs.freedesktop.org/show_bug.cgi?id=108085
> > Signed-off-by: Daniel Drake
> > Signed-off-by: Jian-Hong Pan
>
> Fixes: fd7d6c5c8f3e ("drm/i915: enable FBC on gen9+ too") ?
> Cc: Paulo Zanoni
> Cc: Danie
Em sex, 2019-03-15 às 06:56 +, Tvrtko Ursulin escreveu:
> On 15/03/2019 00:52, Chris Wilson wrote:
> > Quoting José Roberto de Souza (2019-03-15 00:42:35)
> > > We don't have any platform that is composed by 2 or more platforms so
> > > we don't need a mask, lets drop it and remove the actual l
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> The only usage we have for it is for the regs pointer. Save a pointer to
> the set and ack registers instead of the register offsets to remove this
> requirement
Reviewed-by: Paulo Zanoni
>
> Cc: Paulo Zanon
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Get/put functions used outside of uncore.c are updated in the next
> patch for a nicer split
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
I really like this one, replacing a gazillion i915->
't add much value on its own IMHO
(i.e., without the rest of the series), but it still helps intel_uncore
move away from the God Object pattern of dev_priv. I'll add my r-b to
the version with the gvt fix when it's sent.
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Cerao
ase fix all of them :).
I think the s/dev_priv/i915/ here is a little unnecessary since it
inflates the diff even more (when will we settle with a single name?),
but okay let's go with it.
Patch still worth on its own IMHO due to all the dev_priv->uncore to
just uncore reduction.
Revie
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Remove unneeded usage of dev_priv from 1 extra function.
>
Reviewed-by: Paulo Zanoni
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 20 +++
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Use a local variable where it makes sense.
Also worth it on its own IMHO.
Reviewed-by: Paulo Zanoni
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/i
er.
To give a parallel with other parts of the driver, in display code we
tend to pass struct intel_crtc as much as possible and only pass enum
pipe when it doesn't make sense anymore to pass a CRTC. So uncore makes
sense here.
More below:
>
> Cc: Paulo Zanoni
> Signed-of
o the reserved
bits in gen6 is not an issue, then everything else looks correct:
Reviewed-by: Paulo Zanoni
I also couldn't find information about WaRsClearFWBitsAtReset. Don't we
need to update its tags to include the most recent platforms and
ivb/hsw/vlv?
>
> Signed-off-by
lor:
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
> drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> This will allow futher simplifications in the uncore handling.
>
> v2: move register access setup under uncore (Chris)
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Z
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> Save some uncore properties to avoid having to jump back to
> dev_priv every time
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> They now work on uncore, so use raw_uncore_ prefix. Also move them to
> uncore.h
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/
>
> Note that this patch also change the behavior for gen5 with vpgu
> enabled, but this is not an issue since we don't support vgpu on gen5.
>
> v2: split out from previous path, fix check for missing case (Paulo)
Much better as a separate patch. Thanks.
Reviewed-by: Paulo Za
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> Save the HW capabilities to avoid having to jump back to dev_priv
> every time.
>
Reviewed-by: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Cc: Chris Wilson
> ---
&g
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Support added only for async flips on primary plane.
> If flip is requested on any other plane, reject it.
>
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
>
> If any of these are m
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Enable asynchronous flips in i915 for gen9+ platforms.
>
> v2: -Async flip enablement should be a stand alone patch (Paulo)
... and at the very end of the series.
If someone is bisecting the Kernel for some problem unrelated to async
fli
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address reg
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Make the commit call blocking in case of async flips
> so that there is no delay in completing the flip.
>
I'm trying to understand the code. Can you please elaborate more here
in this commit message? Why exactly does the call need to blo
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benc
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address reg
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benc
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> v2: -Move the Async flip enablement to individual patch (Paulo)
>
> v3: -Rebased.
>
> v4: -Add separate plane hook for async flip case (Ville)
>
>
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address reg
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and enable
> the flip done interrupt in IER.
>
> Flip done interrupt is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
>
> Signed-
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Enable support for async flips in I915.
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4
> drivers/gpu/dr
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Support added only for async flips on primary plane.
> If flip is requested on any other plane, reject it.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 29
> 1 file changed, 2
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Send the flip done event in the handler and disable the interrupt.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/i915_irq.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benc
Em Sex, 2017-11-10 às 19:08 +, Lionel Landwerlin escreveu:
> We use to have this fixed per generation, but starting with CNL
> userspace
> cannot tell just off the PCI ID. Let's make this information
> available. This
> is particularly useful for performance monitoring where much of the
> norma
rm/i915: expose command stream timestamp
> frequency to userspace")
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/driv
Em Seg, 2017-12-04 às 15:50 -0200, Paulo Zanoni escreveu:
> Em Seg, 2017-11-13 às 23:34 +, Lionel Landwerlin escreveu:
> > We apply this logic to Gen9 as well. We didn't notice this issue as
> > most part we've encountered so far only use the crystal as source
&g
Em Qua, 2017-12-06 às 20:43 +0530, Lohith BS escreveu:
> Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
> refresh rate to the lowest vrefresh supported by panel, when frame is
> not flipped for more than a Sec.
>
> In kernel, DRRS uses the front buffer tracking infrastructure.
> H
y: Chris Wilson
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>
Em Qua, 2017-12-20 às 20:58 +, Chris Wilson escreveu:
> Include the pending update from the FBC worker in i915_fbc_status.
>
> Signed-off-by: Chris Wilson
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 13 +
> 1 file changed, 9 inser
Em Qui, 2018-04-05 às 15:00 -0700, Dhinakaran Pandiyan escreveu:
> From: Daniel Vetter
>
> The definitions for the error register should be valid on bdw/skl
> too,
> but there we haven't even enabled DE_MISC handling yet.
>
> Somewhat confusing the the moved register offset on bdw is only for
>
Em Seg, 2018-04-09 às 16:23 -0700, James Ausmus escreveu:
> On Wed, Mar 28, 2018 at 02:57:58PM -0700, Paulo Zanoni wrote:
> > This commit introduces the definitions for the ICL clocks and adds
> > the
> > basic functions to the shared DPLL framework. It adds code for the
&
Em Qui, 2018-04-05 às 17:20 -0700, Rodrigo Vivi escreveu:
> On Thu, Feb 22, 2018 at 12:55:10AM -0300, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > This is an important part of the DDI initalization as well as
> > for changing the voltage during DisplayPort
Em Qua, 2018-04-25 às 11:01 -0700, Rodrigo Vivi escreveu:
> On Tue, Apr 24, 2018 at 05:34:14PM -0700, Paulo Zanoni wrote:
> > Em Qui, 2018-04-05 às 17:20 -0700, Rodrigo Vivi escreveu:
> > > On Thu, Feb 22, 2018 at 12:55:10AM -0300, Paulo Zanoni wrote:
> >
according to bspec
and keep them in the same order and rebase (Lucas)
Cc: Michel Thierry
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
intel/intel_bufmgr_gem.c | 2 ++
intel/intel_chipset.h| 27 ++-
intel/inte
is problem on ICL with some
chicken bit, but I still couldn't find which one it is, and it's
better if we just do the right thing here.
Cc: Arthur J Runyan
Cc: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 4 insert
after the pll struct changes.
v6:
- Properly make the unmap function based on encoders_post_disable()
with regarding to checks and iterators.
- Address checkpatch comment on "min = max = x()".
Cc: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_de
Em Qua, 2018-04-25 às 17:29 -0700, Michel Thierry escreveu:
> On 04/25/2018 05:09 PM, Paulo Zanoni wrote:
> > Add the PCI IDs and the basic code to enable ICL. This is the
> > current
> > PCI ID list in our documentation.
> >
> > Kernel commit: d55cb4fa2cf0 (&
Em Seg, 2018-04-30 às 21:12 +0300, Ville Syrjälä escreveu:
> On Fri, Apr 27, 2018 at 04:12:08PM -0700, Paulo Zanoni wrote:
> > For all platforms that run haswell_crtc_enable, our spec tells us
> > to
> > configure the transcoder clocks before it tells us to set pipeconf
>
ing (Ville).
Cc: Arthur J Runyan
Cc: James Ausmus
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Again, I didn't test this patch on every affected platform. Let's see
what the CI
From: Tomasz Lis
In Icelake, there are more engines on which Memory Object Control States need
to be configured. Besides adding Icelake under Skylake config, the patch makes
sure MOCS register addresses for the new engines are properly defined.
Additional patch might be need later, in case the s
eck before merging
Signed-off-by: Paulo Zanoni
---
arch/x86/kernel/early-quirks.c | 18
drivers/gpu/drm/i915/i915_gem_stolen.c | 38 +-
drivers/gpu/drm/i915/i915_reg.h| 1 +
include/drm/i915_drm.h | 4 +++-
4
Em Qui, 2018-05-03 às 12:59 +0300, Joonas Lahtinen escreveu:
> Quoting Paulo Zanoni (2018-05-03 03:23:52)
> > ICL changes the registers and addresses to 64 bits.
> >
> > I also briefly looked at implementing an u64 version of the PCI
> > config
> > read functions,
Em Qua, 2018-05-02 às 22:23 +, Patchwork escreveu:
> == Series Details ==
>
> Series: drm/i915: configure the transcoder clocks before touching
> pipeconf on HSW+ (rev2)
> URL : https://patchwork.freedesktop.org/series/42436/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes f
IZ-9250
CC: sta...@vger.kernel.org
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Signed-off-by: Paulo Zanoni
---
arch/x86/kernel/early-quirks.c | 18 ++
include/drm/i915_drm.h | 4 +++-
2 files changed, 21 insertions
Now that our stolen memory is already reserved by the x86 subsystem
(since commit "x86/gpu: reserve ICL's graphics stolen memory"), make
use of it.
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: x...@kernel.org
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_ge
nay)
> v4:
> - Rebased
> - Renamed patch
> - Improved the ordering of GENs
> - Improved the printing of per-GEN info
> v5: Avoid maybe-unitialized & add comment explaining the lack
> of PM ISR & IIR
>
> Suggested-by: Paulo Zanoni
> Signed-off-by: Oscar Mateo
Lyude
Cc: stevenhoney...@gmail.com
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h| 3 ++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbc.c | 61 ++
drivers/gpu/drm/i915/intel_fifo_underrun.c | 2
216e502aca ("drm/i915/fbc: call intel_fbc_pre_update earlier...")
Signed-off-by: Chris Wilson
Signed-off-by: Paulo Zanoni
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Patrik Jakobsson
Cc: drm-intel-fi...@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_display.c |
estcase: kms_frontbuffer_tracking/fbc-1p-shrfb-fliptrack
Cc: Ville Syrjälä
Cc: Sivakumar Thulasimani
Cc: drm-intel-fi...@lists.freedesktop.org
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_
> cache->plane.rotation != DRM_ROTATE_0) {
> --
> 2.9.3
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
We forgot the "res_blocks += y_tile_minimum" that's described on step
V of our documentation.
Again, this should only affect the Y tiling cases.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-
tches.
This should affect the watermarks for Linear and Y-tiled.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm
o
Cc: Lyude
Cc: Matt Roper
Cc: Mahesh Kumar
Paulo Zanoni (8):
drm/i915: SAGV is not SKL-only, so rename a few things
drm/i915: introduce intel_has_sagv()
drm/i915/kbl: KBL also needs to run the SAGV code
drm/i915/gen9: fix the WaWmMemoryReadLatency implementation
drm/i915/gen9: mini
This should affect linear and X tiled planes on really small htotal
cases. It doesn't seem to be a very feasible case, but let's implement
it since it's on the specification and it's better to have it and
never need than not have it and realize we needed it.
Signed-
tform.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
drivers/gpu/drm/i915/intel_pm.c | 15 +++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d
During watermarks calculations, this value is used in 3 different
places. Only one of them was not using a hardcoded 4. Move the code up
so everybody can benefit from the actual value.
This should only help on situations with Y tiling + 90/270 rotation +
1 or 2 bpp or NV12.
Signed-off-by: Paulo
x27;t seem to be
calling any functions whose name start with a platform name, so the
"intel_" naming scheme seems make more sense than the "firstplatorm_"
naming scheme here.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/
sanitizing implementation from the WA implementation and
fix the WA implementation.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 42 +
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gp
According to BSpec, it's the "core CPUs" that need the code, which
means SKL and KBL, but not BXT.
I don't have a KBL to test this patch on it.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9da8ff2
BSpec was updated and now there's no more "subtract 1" to the
Microsecond Counter Divider field.
It seems this should help fixing some GMBUS issues. I'm not aware of
any specific open bug that could be solved by this patch.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-
awclk() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 37 -
1 file changed, 8 insertions(+), 29
;, which makes a lot more sense. Use the more complete ICL
naming because we will merge the CNP and ICP functions into a single
one, which will introduce the concept of the numerator. That will make
a lot more sense when you read the "num/frac = den" calculation.
Signed-off-by: Paulo Zan
Em Seg, 2018-11-12 às 16:54 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 09, 2018 at 04:23:50PM -0800, Paulo Zanoni wrote:
> > I think I'm probably the one who argued in favor of having separate
> > implementations for both PCHs, but the calculations are actually
> > th
awclk() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
v2: Switch numerator to 1 from 1000 and adjust calculations
accordingly (Ville).
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
d
awclk() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
v2: Switch numerator to 1 from 1000 and adjust calculations
accordingly (Ville).
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
d
;, which makes a lot more sense. Use the more complete ICL
naming because we will merge the CNP and ICP functions into a single
one, which will introduce the concept of the numerator. That will make
a lot more sense when you read the "num/frac = den" calculation.
Reviewed-by: Ville Syrjäl
ille Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 8d74276029e6..810670976e86 100644
--- a/drivers/gpu/drm/i915
Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..18914c4
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