[Intel-gfx] [PATCH 0/3] TV Out patches to make our mode list be according to TV timing standards

. Rodrigo Vivi (3): drm/i915: Fix TV Out refresh rate. drm/i915: Removing TV Out modes. drm/i915: Adding 1080p modes to our TV Out mode list. drivers/gpu/drm/i915/intel_tv.c | 176 ++- 1 files changed, 63 insertions(+), 113 deletions(-) -- 1.7.7.4

[Intel-gfx] [PATCH 1/3] drm/i915: Fix TV Out refresh rate.

TV Out refresh rate was half of the specification for almost all modes. Due to this reason pixel clock was so low for some modes causing flickering screen. Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com --- drivers/gpu/drm/i915/intel_tv.c | 16 1 files changed, 8

[Intel-gfx] [PATCH 2/3] drm/i915: Removing TV Out modes.

These modes are no longer needed or are not according to TV timing standards. Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com --- drivers/gpu/drm/i915/intel_tv.c | 122 --- 1 files changed, 0 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 3/3] drm/i915: Adding 1080p modes to our TV Out mode list.

According to TV Out timing standards, supported 1080p modes were missing. Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com --- drivers/gpu/drm/i915/intel_tv.c | 72 +++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915: Removing TV Out modes.

These modes are no longer needed or are not according to TV timing standards. Intel PRM Vol 3 - Display Registers Updated - Section 5 TV-Out Programming / 5.2.1 Television Standards / 5.2.1.1 Timing tables Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com --- drivers/gpu/drm/i915/intel_tv.c

[Intel-gfx] [PATCH 2/2] drm/i915: Adding 1080p modes to our TV Out mode list.

Adding 1080p supported modes according to new PRM version which is internal for now. Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com --- drivers/gpu/drm/i915/intel_tv.c | 72 +++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/drivers/gpu

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix TV Out refresh rate.

Vivi rodrigo.v...@gmail.com wrote: TV Out refresh rate was half of the specification for almost all modes. Due to this reason pixel clock was so low for some modes causing flickering screen.  Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com And  These modes are no longer needed

Re: [Intel-gfx] Problem Intel i915 driver, i3 2010T, HDMI output modes problems

... ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx

Re: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes

-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] WG: Interlaced mode on intel Clarkdale only colored stripes

. Before I used the drm-intel-next branch. I downloaded the latest tar.gz file and didn't use git to checkout the branch. Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] The git repo is right, but are you sure you are using the remotes/origin/interlaced branch? It is strange that you couldn't see any

[Intel-gfx] [PATCH] drm/i915: Don't pretend ips is always enabled on BDW.

to be enabled. Even if the current status is impossible to be ascertain. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915: Fix some NUM_RING iterators

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jun 27, 2014 at 3:09 PM, Ben Widawsky benjamin.widaw...@intel.com wrote: There are some cases in the code where we need to know how many rings to iterate over, but cannot use for_each_ring(). These are always error cases which happen

Re: [Intel-gfx] [PATCH] drm/i915: flush delayed_resume_work when suspending

-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jun 27, 2014 at 2:51 PM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com It is possible that, by the time we run i915_drm_freeze(), delayed_resume_work was already queued but did not run yet. If it still didn't run

[Intel-gfx] [PATCH] drm/i915: Don't pretend ips is always enabled on BDW.

paulo.r.zan...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a93b3bf..380be89 100644

Re: [Intel-gfx] [PATCH] drm/i915: flush delayed_resume_work when suspending

On Mon, Jun 30, 2014 at 12:22 PM, Paulo Zanoni przan...@gmail.com wrote: 2014-06-27 19:30 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com: I have the feeling the safest side would be disable rc6 on resume instead of force its enabling... or am I missing something? It will be enabled

[Intel-gfx] [PATCH 1/3] drm/i915: Fix VCS2's ring name.

It just fix a typo. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2faef26..c3f96a1 100644

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce dual_bsd_ring parameter.

and use one specific ring given at boot time. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 34 ++ drivers/gpu/drm/i915/i915_params.c | 6 ++ 3 files

[Intel-gfx] [PATCH 3/3] drm/i915: Updating comments.

ring index calculation table was out of date after other rings were added, although the formula is flexible and scale when adding new rings. So this patch just update the comments and add a brief explanation why to use sync_seqno[ring index]. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH 01/10] drm/i915: Make semaphore updates more precise

) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com (v1) Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 27 +-- 1 file

[Intel-gfx] [PATCH 02/10] drm/i915: gen specific ring init

values in for the mbox info. v2: v1 had a stale commit message v3: Move everything in the is_semaphore_enabled() check v4: VCS2 rebase Remove double assignment of signal in render ring (Ville) v5: Adding missed VCS2 signal init on gen8+ (Rodrigo) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH 04/10] drm/i915/bdw: implement semaphore wait

the other ring's ring-id (Chris) v3: Add missing VCS2 gen8_ring_wait init besides s/ring_buffer/engine_cs (Rodrigo) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 10/10] drm/i915: Enable semaphores on BDW

Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6eb45ac..1f84f88 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm

[Intel-gfx] [PATCH 07/10] drm/i915/bdw: collect semaphore error state

capture coding style consistent (Ville) Do the proper math for the signal offset (Ville) v6: Fix small conflicts on rebase and s/ring_buffer/engine_cs (Rodrigo) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v

[Intel-gfx] [PATCH 03/10] drm/i915/bdw: implement semaphore signal

table * remove WARN_ON Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 5 +- drivers/gpu

[Intel-gfx] [PATCH 08/10] drm/i915: semaphore debugfs

. v2 (Rodrigo): * Iterate only on active rings. * s/ring_buffer/engine_cs. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 71

[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

Ipehr just carries Dword 0 and on Gen 8, offsets are located on Dword 2 and 3 of MI_SEMAPHORE_WAIT. This implementation was based on Ben's work and on Ville's suggestion for Ben Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 09/10] drm/i915/bdw: poll semaphores

this as an W/A for GT3. However semaphores didn't worked in my BDW GT2 on Signal Mode. So pool mode is definitely needed. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Tested-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 06/10] drm/i915: Extract semaphore error collection

From: Ben Widawsky benjamin.widaw...@intel.com v2: s/ring_buffer/engine_cs (Rodrigo) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 30

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Move compressed_fb to static allocation

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Thu, Jun 19, 2014 at 12:06 PM, Ben Widawsky benjamin.widaw...@intel.com wrote: We are already using the size to determine whether or not to free the object, so there is no functional change there. Almost everything else has changed

Re: [Intel-gfx] [PATCH] drm/i915: Try harder to get FBC

Jani, please ignore the 4th patch on this series and merge the 3 I've reviewed and tested already. They are essential to allow FBC work on BDW without changing bios configuration and allow PC7 residency. Thanks, Rodrigo. On Mon, Jun 30, 2014 at 10:41 AM, Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH] drm/i915: Fix VCS2's ring name.

It just fix a typo. v2: removing underscore to let this like all other ring names (Oscar) Cc: Oscar Mateo oscar.ma...@intel.com Reviewed-by (v1): Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1

[Intel-gfx] [PATCH 00/10] drm-intel-collector - update

This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector It was 4 rounds out of date what made it hard to get old patches. However Daniel and Jani didn't leave many patches behind. 0 on Apr 4 - Apr 16 1 on Apr 16 - May 6 2 on

[Intel-gfx] [PATCH 01/10] drm/i915: Bring UP Power Wells before disabling RC6.

...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d771e82..1e4611a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b

[Intel-gfx] [PATCH 02/10] drm/i915: Don't save/restore RS when not used

From: Ben Widawsky benjamin.widaw...@intel.com Cc: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions

[Intel-gfx] [PATCH 00/10] drm-intel-collector - update

This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector It was 4 rounds out of date what made it hard to get old patches. However Daniel and Jani didn't leave many patches behind. 0 on Apr 4 - Apr 16 1 on Apr 16 - May 6 2 on

[Intel-gfx] [PATCH 03/10] drm/i915: Upgrade execbuffer fail after resume failure to EIO

=76554 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 04/10] drm/i915: Add property to set HDMI aspect ratio

jesse.bar...@intel.com Cc: Vijay Purushothaman vijay.a.purushotha...@intel.com Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 10/10] drm/i915/vlv: T12 eDP panel timing enforcement during reboot.

: removed redundant pr_crit(), commented magic value for pp_div_reg Ver3: moved SYS_RESTART check earlier, new name for pp_div. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 42

[Intel-gfx] [PATCH 09/10] drm/i915/bdw: Always issue a force restore

Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 633e318..61b60b6 100644

[Intel-gfx] [PATCH 06/10] drm/i915: honour forced connector modes

-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_fbdev.c | 33 - 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 226fbc7..34c1a3d 100644 --- a/drivers

Re: [Intel-gfx] [PATCH 09/10] drm/i915/bdw: Always issue a force restore

Thanks Please just ignore this one for now. It will be removed on next round. On Thu, Jul 3, 2014 at 5:38 PM, Ben Widawsky benjamin.widaw...@intel.com wrote: On Thu, Jul 03, 2014 at 05:33:05PM -0400, Rodrigo Vivi wrote: From: Ben Widawsky benjamin.widaw...@intel.com The PDPs seem to get

[Intel-gfx] [PATCH] drm/i915: Implement MI decode for gen8

Syrjälä ville.syrj...@linux.intel.com Cc: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 42 ++--- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.

this patch introduces a persistent way to enable false color over debugfs. v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested Cc: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 42

[Intel-gfx] [PATCH 11/11] drm/i915: Enable PSR by default.

frontbuffer tracking support and correct locks on place we can enabled this feature by default. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers

[Intel-gfx] [PATCH 03/11] drm/i915: Track the psr dp connector in dev_priv-psr.enabled

From: Daniel Vetter daniel.vet...@ffwll.ch Trying to fish that one out through looping is a bit a locking nightmare. So just set it and use it in the work struct. v2: - Don't Oops in psr_work, spotted by Rodrigo. - Fix compile warning. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off

[Intel-gfx] [PATCH 02/11] drm/i915: Add a FIXME about drrs/psr interactions

From: Daniel Vetter daniel.vet...@ffwll.ch Can't review this right now due to lack of DRRS code. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Cc: Vandana Kannan vandana.kan...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH 09/11] drm/i915: Improve PSR debugfs output

From: Daniel Vetter daniel.vet...@ffwll.ch Add busy_frontbuffer_bits and locking. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++ 1 file

[Intel-gfx] [PATCH 05/11] drm/i915: Lock down psr sw/hw state tracking

From: Daniel Vetter daniel.vet...@ffwll.ch Make sure we track the sw side (psr.active) correctly and WARN everywhere it might get out of sync with the hw. v2: Fixup WARN_ON logic inversion, reported by Rodrigo. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter

[Intel-gfx] [PATCH 08/11] drm/i915: Fix up PSR frontbuffer tracking

. - Comments Chris requested to clarify the code. v7: Fix conflict on rebase (Rodrigo) Cc: Chris Wilson ch...@chris-wilson.co.uk Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu

[Intel-gfx] [PATCH 07/11] drm/i915: Add locking to psr code

tracking. The other nasty bit that had to go was the delayed work cancle in psr_exit. Which means a bunch of races just became a bit more likely, but mea culpa. v2: Fixup HAS_PSR checks, resulting in uninitialized mutex issues. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel

[Intel-gfx] [PATCH 01/11] drm/i915: Run psr_setup unconditionally

simpler to just remove code instead. v2: Properly bail out of psr exit if psr isn't enabled. Spotted by Rodrigo. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 06/11] drm/i915: More checks for psr.enabled

(Rodrigo) Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu

[Intel-gfx] [PATCH 10/11] drm/i915: Remove redundant HAS_PSR checks

Wilson. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 14 -- 1 file changed, 14 deletions(-) diff

[Intel-gfx] [PATCH 04/11] drm/i915: Don't try to disable psr harder from the work item

From: Daniel Vetter daniel.vet...@ffwll.ch It's disabled already except when we've raced. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 4 +--- 1 file

Re: [Intel-gfx] [PATCH] drm,drm/i915: Export cmdline mode parsing

___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx

Re: [Intel-gfx] [PATCH] drm: Perform cmdline mode parsing during connector initialisation

___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http

[Intel-gfx] [PATCH 01/11] drm/i915: Bring UP Power Wells before disabling RC6.

...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 780c3ab..4fb8917 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b

[Intel-gfx] [PATCH 00/11] drm-intel-collector - update

This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector Here goes the update list in order for better reviewers assignment: Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer: Paulo Zanoni

[Intel-gfx] [PATCH 10/11] drm/i915: Bring GPU Freq to min while suspending.

From: Deepak S deepa...@linux.intel.com We might be leaving the PGU Frequency (and thus vnn) high during the suspend. Flusing the delayed work queue should take care of this. Signed-off-by: Deepak S deepa...@linux.intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm

[Intel-gfx] [PATCH 04/11] drm/i915: Add property to set HDMI aspect ratio

jesse.bar...@intel.com Cc: Vijay Purushothaman vijay.a.purushotha...@intel.com Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 06/11] drm/i915: Don't promote UC to WT automagically

-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e5d4d73..c3e7e8f

[Intel-gfx] [PATCH 02/11] drm/i915: Don't save/restore RS when not used

From: Ben Widawsky benjamin.widaw...@intel.com v2: fix conflict on rebase. Cc: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 10 ++ 1 file changed, 6

[Intel-gfx] [PATCH 03/11] drm/i915: Upgrade execbuffer fail after resume failure to EIO

=76554 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 05/11] drm/i915: honour forced connector modes

-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_fbdev.c | 33 - 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index f475414..5d879d18 100644

[Intel-gfx] [PATCH 07/11] drm/i915: Refactor the physical and virtual page hws setup

From: Chris Wilson ch...@chris-wilson.co.uk We duplicated the legacy physical HWS setup routine for no good reason. Combine it with the more recent virtual HWS setup for simplicity. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH 08/11] drm/i915: clean up PPGTT checking logic

intel_enable_ppgtt() function. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 - 3 files changed, 5

[Intel-gfx] [PATCH 09/11] drm/i915: re-order ppgtt sanitize logic v2

-detect case since we already caught the no PPGTT case early on (Jesse) Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 25 + 1 file changed, 13 insertions(+), 12 deletions

Re: [Intel-gfx] [PATCH 2/5] drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com So don't write it, otherwise we will trigger unclaimed register errors. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni

Re: [Intel-gfx] [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Thu, Jul 10, 2014 at 12:31 PM, Paulo Zanoni przan...@gmail.com wrote: 2014-07-08 11:58 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Tue, Jul 08, 2014 at 11:15:03AM -0300, Paulo Zanoni wrote: 2014-07-07 18:23 GMT-03:00 Daniel Vetter dan

Re: [Intel-gfx] [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c so we can reuse the nice IRQ macros we have

Re: [Intel-gfx] [PATCH 4/5] drm/i915: reorganize the unclaimed register detection code

mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx The rest looks good. With that fixed and probably with comment removed as Daniel mentioned, feel free to use: Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com -- Rodrigo Vivi Blog: http

Re: [Intel-gfx] [PATCH 5/5] drm/i915: BDW can also detect unclaimed registers

Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com By the time I wrote this patch, it allowed me to catch some problems. But due to patch reordering - in order to prevent fake

[Intel-gfx] [PATCH] drm/i915: Fix semaphore_seqno and semaphore_mboxes sizes

Otherwise some iteractions depending on the current number of active rings could overflow. Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Intel-gfx] [PATCH] drm/i915: Fix semaphore_seqno and semaphore_mboxes sizes

just ignore this one.. On Thu, Jul 17, 2014 at 5:00 AM, Rodrigo Vivi rodrigo.v...@intel.com wrote: Otherwise some iteractions depending on the current number of active rings could overflow. Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.

; * bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; * vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; * vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; */ Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 9 + 1

[Intel-gfx] [PATCH] drm/i915: print full error ring semaphore mboxes and sync.

With the increasing number of rings, we probably have more information to print than we were printing. Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++ 1 file changed, 6 insertions

[Intel-gfx] [PATCH] drm/i915: print full error ring semaphore mboxes and sync.

With the increasing number of rings, we probably have more information to print than we were printing. v2: Loop only over active rings and print info with ring names. Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.

; * bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; * vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; * vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; */ v2: Skip when from == to (Damien). Cc: Damien Lespiau damien.lesp...@intel.com Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.

continue instead of return (Rodrigo). Cc: Damien Lespiau damien.lesp...@intel.com Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git

[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.

continue instead of return (Rodrigo). v4: avoid all unecessary computation (Damien). reduce idx to loop scope (Damien). Cc: Damien Lespiau damien.lesp...@intel.com Cc: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.

GTIER and DEIER doesn't have same interface on HSW so this or operation makes the information provided useless. Cc: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.

On Wed, Jul 30, 2014 at 10:53 AM, Paulo Zanoni przan...@gmail.com wrote: 2014-07-28 12:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com: GTIER and DEIER doesn't have same interface on HSW so this or operation makes the information provided useless. Cc: Paulo Zanoni paulo.r.zan

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.

On Wed, Jul 30, 2014 at 11:09 AM, Paulo Zanoni przan...@gmail.com wrote: 2014-07-28 12:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com: BDW has many other Display Engine interrupts and GT interrupts registers. Collecting it properly on gpu_error_state. On debugfs all was properly listed

[Intel-gfx] [PATCH 1/2] drm/i915: Introduce FBC False Color for debug purposes.

Cc: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 42 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 2/2] drm/i915: FBC flush nuke for BDW

debugs. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b3d8f76..3e06a1b 100644 --- a/drivers

[Intel-gfx] [PATCH] drm/i915: Skip Stolen Memory first page.

WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_stolen.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b

[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.

Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 42 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 3 +++ 4 files

[Intel-gfx] [PATCH] drm/i915: Skip Stolen Memory first page.

WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle v2: Improve variable names and fix allocated size. Reviewed-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_stolen.c | 15 ++- 1

[Intel-gfx] [PATCH] drm/i915: FBC flush nuke for BDW

debugs. v2: Fix rebase conflict. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index

[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.

/!HAS_FBC (Ville) Cc: Ville Syrjälä ville.syrj...@linux.intel.com Reviewed-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 42 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu

[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.

that we should reorganize the whole function, but I'll respect the comment that ask to not touch the order and let this organization work to be done later. Cc: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1

[Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.

: https://bugs.freedesktop.org/show_bug.cgi?id=81701 v2: Fix small issues of first version and don't read DEIER regs when pipe's power well is disabled Cc: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 4

[Intel-gfx] [PATCH] drm/i915: Fix error state collecting

Fix signal_offset when recording semaphore state on BDW. Reviewed-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.

that we should reorganize the whole function, but I'll respect the comment that ask to not touch the order and let this organization work to be done later. v3: moving VLV check to the right place. Cc: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

[Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.

: https://bugs.freedesktop.org/show_bug.cgi?id=81701 v2: Fix small issues of first version and don't read DEIER regs when pipe's power well is disabled v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection Cc: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Rodrigo

[Intel-gfx] [PATCH] drm/i915: FBC flush nuke for BDW

: Fix rebase conflict. v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c| 3 +++ drivers/gpu/drm/i915/intel_pm.c | 10

[Intel-gfx] [PATCH 2/7] drm/i915: Add thread stall DOP clock gating workaround on Broadwell.

From: Kenneth Graunke kenn...@whitecape.org Ben and I believe this will be necessary on production hardware. Signed-off-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 1/7] drm/i915/bdw: Always issue a force restore

Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 3b99390..56f7b1e 100644

[Intel-gfx] [PATCH 6/7] drm/i915: BDW Semaphore signal with Post Sync

. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 3 +++ drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm

[Intel-gfx] [PATCH 3/7] drm/i915/bdw: MI_FLUSH_DW a qword instead of dword

series, so it won't be easily applied, I'd guess. Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 95 + 1 file changed, 74 insertions(+), 21 deletions(-) diff --git

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