mments (Michal)
v10: Introducing enable_guc modparam
Applying review comments (Michal)
Signed-off-by: Sujaritha Sundaresan
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
With new GuC firmwares (SKL v9.33, BXT v9.29, KBL v9.39) available now
at 01.org downloads, let us update the default firmware versions.
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Sagar Arun Kamble (3):
drm/i915/guc: Change default
C internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
- Aggressive DCC implementation for supported platforms.
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood
es for OCA using special Control
Bit
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++--
1 file
rrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood
On 11/29/2017 12:41 PM, Joonas Lahtinen wrote:
On Wed, 2017-11-29 at 11:47 +0530, Sagar Arun Kamble wrote:
With new GuC firmwares (SKL v9.33, BXT v9.29, KBL v9.39) available now
at 01.org downloads, let us update the default firmware versions.
I thought the agreement was for them to be at
to intel_engines_reset_default_submission.
(Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Sagar Arun Kamble
Cc: Sagar Arun Kamble
Reviewed-by: Chris Wilson (v2)
---
drivers/gpu/drm/i915/i915_pmu.c | 11 ---
drivers/gpu/drm/i915/intel_engine_cs.c | 8 +---
drivers/gpu/drm/i
to intel_engines_reset_default_submission.
(Chris Wilson)
v5: Move flag setting to logical_ring_setup.
v6: intel_engines_reset_default_submission is the wrong place to set the
flag - it needs to be in execlists_set_default_submission. (Sagar)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Sagar Arun Kamble
Cc: Sagar A
On 11/28/2017 9:12 PM, Michal Wajdeczko wrote:
Instead of trying different seq_puts messages, lets use common
-ENODEV error code to indicate missing/unsupported feature.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
On 11/29/2017 6:31 AM, Yaodong Li wrote:
On 11/16/2017 08:00 PM, Sagar Arun Kamble wrote:
On 11/17/2017 3:17 AM, Michal Wajdeczko wrote:
On Thu, 16 Nov 2017 08:34:01 +0100, Sagar Arun Kamble
wrote:
Typo in the subject.
GLK showing failure to load GuC with this approach on CI.
On 11/15
On 11/29/2017 5:44 PM, Michal Wajdeczko wrote:
On Tue, 28 Nov 2017 11:41:57 +0100, Sagar Arun Kamble
wrote:
On 11/28/2017 1:24 AM, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission&quo
With new GuC firmwares (SKL v9.33, BXT v9.29, KBL v9.39) merged now
in linux-firmware.git, let us update the default firmware versions.
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Sagar Arun Kamble (3):
drm/i915/guc: Change default
rrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood
C internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
- Aggressive DCC implementation for supported platforms.
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood
es for OCA using special Control
Bit
v2: Rebase. Updated commit message.
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++--
1 file
On 11/30/2017 8:34 AM, John Harrison wrote:
On 11/24/2017 6:12 AM, Chris Wilson wrote:
Quoting Michał Winiarski (2017-11-24 12:37:56)
Since we see the effects for GuC preeption, let's gather some evidence.
(SKL)
intel_guc_send_mmio latency: 100 rounds of gem_exec_latency --r '*-preemption'
On 11/30/2017 12:45 PM, John Harrison wrote:
On 11/29/2017 10:19 PM, Sagar Arun Kamble wrote:
On 11/30/2017 8:34 AM, John Harrison wrote:
On 11/24/2017 6:12 AM, Chris Wilson wrote:
Quoting Michał Winiarski (2017-11-24 12:37:56)
Since we see the effects for GuC preeption, let's gather
On 12/1/2017 12:40 AM, Chris Wilson wrote:
Quoting Patchwork (2017-11-30 18:37:38)
== Series Details ==
Series: series starting with [1/6] drm/i915/huc: Move firmware selection to
init_early
URL : https://patchwork.freedesktop.org/series/34694/
State : failure
WARNING: Long output truncat
led for given platform based on
hardware/firmware availability or preference.
Explicit enabling any of the GuC features makes GuC load
a required step, fallback to non-GuC mode will not be
supported.
v2: Don't use -EIO
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc
GPU condition.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
Ok, keeping -EIO to mean something special is a good idea. So if upload
now fails, we abort loading of the driver with ENOEXEC.
Is that sensible? Let's say due to fs corruption, or
Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
+ struct intel_huc *huc = &dev_priv->huc;
int ret, attempts;
if (!USES_G
On 12/5/2017 7:28 PM, Lionel Landwerlin wrote:
On 15/11/17 12:25, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2017-11-15 12:13:51)
#include
#include
@@ -2149,6 +2150,14 @@ struct i915_perf_stream {
* @oa_config: The OA configuration used by the stream
On 12/5/2017 7:52 PM, Lionel Landwerlin wrote:
On 15/11/17 12:13, Sagar Arun Kamble wrote:
From: Sourab Gupta
Currently, we have the ability to only forward the GPU timestamps in the
samples (which are generated via OA reports). This limits the ability to
correlate these samples with the
trace_clock in ftrace.
I'll look at adding some tests for this too.
Thanks,
-
Lionel
On 15/11/17 12:13, Sagar Arun Kamble wrote:
We can compute system time corresponding to GPU timestamp by
taking a
reference point (CPU monotonic time, G
st PTR_ERR (Chris)
fetch/fini only if required (Michal)
fix wrong break (Sagar)
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
/**
@@ -186,6 +190,7 @@ static void guc_disable_communication(struct intel_guc *guc)
int intel_uc_init
On 12/6/2017 9:31 PM, Lionel Landwerlin wrote:
On 15/11/17 12:13, Sagar Arun Kamble wrote:
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1447,6 +1447,12 @@ enum drm_i915_perf_property_id {
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
+ * The value of this
On 12/7/2017 1:25 AM, Lionel Landwerlin wrote:
On 15/11/17 12:13, Sagar Arun Kamble wrote:
From: Sourab Gupta
The OA reports contain the least significant 32 bits of the gpu
timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu
58072430542 device time: 1512308515100398084
samples (329, 506) = 6494ns>
I'll build the GPUTop parts and see if the results make sense.
Thanks!,
-
Lionel
On 15/11/17 12:13, Sagar Arun Kamble wrote:
We can compute system time corresponding to GPU timestamp by taking a
reference point (CPU mon
On 12/22/2017 10:45 AM, Sagar Arun Kamble wrote:
On 12/7/2017 1:32 AM, Lionel Landwerlin wrote:
I've put together some trival IGT tests :
https://github.com/djdeath/intel-gpu-tools/commits/wip/djdeath/cpu-timestamps
With a few changes which I pointed in the review :
https://githu
On 12/7/2017 6:18 AM, Robert Bragg wrote:
On Wed, Nov 15, 2017 at 12:13 PM, Sagar Arun Kamble
mailto:sagar.a.kam...@intel.com>> wrote:
We can compute system time corresponding to GPU timestamp by taking a
reference point (CPU monotonic time, GPU timestamp) and then
On 12/21/2017 6:29 PM, Lionel Landwerlin wrote:
Some more findings I made while playing with this series & GPUTop.
Turns out the 2ms drift per second is due to timecounter. Adding the
delta this way :
https://github.com/djdeath/linux/commit/7b002cb360483e331053aec0f98433a5bd5c5c3f#diff-9b74b
"GEM_BUG_ON on invoking GuC reset function for non-GuC
platforms"
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --g
On 11/29/2017 6:03 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Wire up the engine busy stats accounting to the GuC submission backend.
Since there is not
no
context out interrupt we need to place the accounting
callbacks per-request in order to correctly pair with user interrupts.
v2
On 12/22/2017 3:46 PM, Lionel Landwerlin wrote:
On 22/12/17 09:30, Sagar Arun Kamble wrote:
On 12/21/2017 6:29 PM, Lionel Landwerlin wrote:
Some more findings I made while playing with this series & GPUTop.
Turns out the 2ms drift per second is due to timecounter. Adding the
delta
n
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
with above changes
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
dr
n
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
On 12/28/2017 10:43 PM, Lionel Landwerlin wrote:
On 26/12/17 05:32, Sagar Arun Kamble wrote:
On 12/22/2017 3:46 PM, Lionel Landwerlin wrote:
On 22/12/17 09:30, Sagar Arun Kamble wrote:
On 12/21/2017 6:29 PM, Lionel Landwerlin wrote:
Some more findings I made while playing with this
Since ring frequency programming needs consideration of both IA and GT
frequency requests I think keeping the logic
to program the ring frequency table in driver that monitors both IA/GT
busyness and power budgets like intel_ips
will be more appropriate. intel_ips is relying on global load derive
wakeref and skipping relay release during
uc_fini.
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Radoslaw Szwichtenberg
Cc: Chris Wilson
Cc: Joonas Lahtinen
Sagar Arun Kamble (12):
drm/i915: Export low level PM IRQ functions to use from GuC functions
drm/i915/guc: Move GuC interrupts
In order to separate GuC IRQ handling functions from i915_irq.c we need
to export the low level pm irq handlers. Export pm_iir, reset_pm_iir and
enable/disable_pm_irq functions.
v2-v3: Rebase.
Suggested-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele
-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin #v2
---
drivers/gpu/drm/i915/i915_params.c | 3 ++-
drivers/gpu/drm/i915/intel_guc_log.c | 1 +
2 files changed, 3 insertions(+), 1
intel_guc_log_runtime_destroy. (Tvrtko)
Added intel_guc_log_runtime_create to separate the creation part as well.
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc.c | 8 +++-
drivers
GuC interrupts handling functions are GuC specific functions hence update
the parameter from dev_priv to intel_guc struct.
v2-v3: Rebase.
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by
the series. (Tvrtko)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu
-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 70 +--
drivers/gpu/drm/i915/intel_drv.h | 3
Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index
reset as well.
Further restructuring of runtime_pm_enable/disable_interrupts and
suspend/restore_guc_interrupts will be done in upcoming patches.
v2: Rebase.
v3: Updated suspend/restore with the new low level get/put functions.
(Tvrtko)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc
This patch introduces i915 internal state variable in GuC log struct,
"level" which will be copied from guc_log_level modparam during i915
load and thereafter be available for user updates. This will make
guc_log_level parameter immutable.
Suggested-by: Tvrtko Ursulin
Signed-off-by:
Also 1) revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
2) fix RPM resume interrupt enabling w.r.t GuC resume
3) disable guc log streaming DRM logs
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/
check in i915_guc_log_unregister to be based on
guc_log_level. (Michal Wajdeczko)
v3: Rebase. Made all GuC log related functions depend only log level.
Updated uC init w.r.t enabling of GuC interrupts. Commit message update.
Rebase w.r.t guc_log_level immutable changes. (Tvrtko)
Signed-off-by: Sagar Arun Ka
spend/resume. (Tvrtko)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +
drivers/gpu/drm/i915/intel_guc.c | 47 +++-
dr
On 1/4/2018 10:01 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:23:05 +0100, Chris Wilson
wrote:
Quoting Sagar Arun Kamble (2018-01-04 16:21:45)
GuC interrupts handling functions are GuC specific functions hence
update
the parameter from dev_priv to intel_guc struct.
v2-v3: Rebase
On 1/4/2018 9:59 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2018-01-04 16:21:54)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d..c8460c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2659,6 +2659,8
On 1/4/2018 10:22 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:46 +0100, Sagar Arun Kamble
wrote:
guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info.
^^^
Extra "."
in parameter descr
On 1/4/2018 10:45 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:51 +0100, Sagar Arun Kamble
wrote:
With GuC log level set properly only for cases where GuC is loaded we
can
remove the GuC submission checks from flush_guc_logs and
guc_log_register,
unregister and uc_fini_hw
On 1/4/2018 10:52 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:45 +0100, Sagar Arun Kamble
wrote:
GuC interrupts handling functions are GuC specific functions hence
update
the parameter from dev_priv to intel_guc struct.
v2-v3: Rebase.
Signed-off-by: Sagar Arun Kamble
Cc
On 1/4/2018 11:09 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:52 +0100, Sagar Arun Kamble
wrote:
This patch adds support to enable/disable GuC interrupts for different
features without impacting other's need. Currently GuC log capture and
CT buffer receive mechanisms use th
On 1/4/2018 11:19 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:53 +0100, Sagar Arun Kamble
wrote:
In order to override the disable/enable control of GuC interrupts during
suspend/reset cycle we are creating two new functions suspend/restore
guc_interrupts which check if interrupts
Also 1) revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
2) fix RPM resume interrupt enabling w.r.t GuC resume
3) disable guc log streaming DRM logs
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/
. Using
readily available guc struct instead of referencing via dev_priv. (Michal)
s/intel_*_guc_interrupts/intel_guc_*_interrupts. (Chris)
Suggested-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas
ned-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_guc.c | 6 +++---
drivers/gpu/drm/i915/intel_guc_
the series. (Tvrtko)
v4: Rebase.
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
Szwichtenberg
Cc: Chris Wilson
Cc: Joonas Lahtinen
Sagar Arun Kamble (9):
drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to
intel_guc.c
drm/i915/guc: Fix GuC interrupts disabling with logging
drm/i915/guc: Separate creation/release of runtime logging data from
-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915
spend/resume. (Tvrtko)
v4: Rebase. Removed comments about logging being sole user of interrupts.
s/guc_intr_client/intel_guc_intr_client. Reverted function names to
enable/disable_interrupts from get/put_interrupts as applicable. (Michal)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Da
(Michal)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_guc.c | 30 --
drivers/gpu/drm/i915
: Rebase. Prepared new functions intel_guc_log_*_interrupts to reduce
log level checks. (Michal)
Added HAS_GUC checks to i915_guc_log_register/unregister as the parameter
is not sanitized. (Sagar)
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
C
intel_guc_log_runtime_destroy. (Tvrtko)
Added intel_guc_log_runtime_create to separate the creation part as well.
v4: Rebase.
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc.c | 8
On 1/5/2018 10:24 AM, Sagar Arun Kamble wrote:
On 1/4/2018 10:22 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:21:46 +0100, Sagar Arun Kamble
wrote:
guc_log_level parameter takes effect when GuC is loaded which is
controlled through enable_guc parameter. Add this relation info
On 1/5/2018 3:22 AM, Yaodong Li wrote:
On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote:
Since ring frequency programming needs consideration of both IA and
GT frequency requests I think keeping the logic
to program the ring frequency table in driver that monitors both
IA/GT busyness and
On 1/5/2018 2:42 PM, Patchwork wrote:
== Series Details ==
Series: GuC Interrupts/Log updates (rev3)
URL : https://patchwork.freedesktop.org/series/32179/
State : failure
== Summary ==
Series 32179v3 GuC Interrupts/Log updates
https://patchwork.freedesktop.org/api/1.0/series/32179/revision
On 1/6/2018 5:53 AM, Yaodong Li wrote:
On 01/05/2018 02:15 AM, Sagar Arun Kamble wrote:
On 1/5/2018 3:22 AM, Yaodong Li wrote:
On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote:
Since ring frequency programming needs consideration of both IA and
GT frequency requests I think keeping the
on top of the WA refactoring
Cc: Sagar Arun Kamble
Cc: Praveen Paneri
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff
On 4/20/2018 3:24 PM, Mika Kuoppala wrote:
We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When this happens
in a wait_for loop, we return timeout errorneously
much earlier than what the real wallcl
On 4/20/2018 4:09 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2018-04-20 11:23:50)
On 4/20/2018 3:24 PM, Mika Kuoppala wrote:
We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When t
bugfs interfaces.
A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.
v2: Use intel_slpc_active instead of HAS_SLPC (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file
d-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 184
drivers/gpu/drm/i915/intel_slpc.c | 19
drivers/gpu/drm/i915/intel_slpc.h | 1 +
3 files changed, 204 insertions(+)
diff --git a/drivers/gp
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other GENs
this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case of
disabling of RPS in gen9_enable_rps.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915
Added SLPC state update during disable, suspend and reset.
Changed semantics of reset. It is supposed to just disable. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 22 +++---
1 file changed, 19 insert
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
v3: Avoid magic numbers (Jon Bloomfield)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 252
place HAS_SLPC with intel_slpc_active (Paulo)
v3: Avoid magic numbers (Nick)
Use a function for repeated code (Jon)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gp
er as SLPC gets disabled in
disable/suspend.(Sagar)
v6: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i9
d-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc.h| 6 ++
drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++---
From: Tom O'Rourke
v2: fix whitespace (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gp
chat, Marc
Cc: Jeff McGee
Sagar Arun Kamble (7):
drm/i915: Remove RPM suspend dependency on rps.enabled and related
changes
drm/i915: Check GuC load status for Host to GuC action and SLPC status
drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
drm/i915/slpc: Only Enable
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.
Signed-off-by: Sagar Arun K
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v2: fix whitespace (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
d
on in earlier patch.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 75b360f..6765edf 10
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 63 ++--
drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
drivers/gpu/drm/i915/intel_slpc.c | 28 -
drivers/gpu/drm/i915/intel_slpc.h | 73
ned-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 16
drivers/gpu/drm/i915/intel_guc.h | 2 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submissi
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 26cea21..2bfb30f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
v5: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kambl
variable
to determine if it is active as it not just dependent on shared
data setup.
Rebase with guc_allocate_vma related changes.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_drv.h | 7 ++-
drivers/gpu/drm/i915/intel_guc.h | 2 +
igned-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
ind
ction change.(Sagar)
Updating SLPC enabled status. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 29 +
drivers/gpu/drm/i915/intel_slpc.h | 14 ++
2 files changed, 43 insertions(+)
di
d-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drive
This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
From: Tom O'Rourke
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v2: use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar A
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar A
v2: Updated tasks and frequency post reset.
v3: Added DFPS param update for MAX_FPS and FPS Stall.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 29 +
drivers/gpu/drm/i915/intel_slpc.h | 5
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