Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 10 --
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++
3 files changed, 44
register.
3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |7 ++
drivers/gpu/drm/i915/intel_dsi.c | 185
...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 53 +
drivers/gpu/drm/i915/intel_display.c |6 +++-
drivers/gpu/drm/i915/intel_opregion.c |1 +
4 files
From: Shashank Sharma shashank.sha...@intel.com
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915
for transcoder.
3. BXT can select PIPE for MIPI transcoders.
4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
even if only one is being used.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h
From: Shashank Sharma shashank.sha...@intel.com
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu
(0x1b 24)
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 28 +++---
drivers/gpu/drm/i915/intel_drv.h |2 +
drivers/gpu/drm/i915
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b
/bxt: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (1):
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 35 ++
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 85 +-
4 files
clock and dividers
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
Signed-off-by: Uma Shankar uma.shan...@intel.com
Signed-off
option to get 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 51 ++
drivers/gpu/drm/i915/intel_dsi.c
type and
calls appropriate core pll disable function.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c
-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/intel_dsi.c | 67 --
2 files changed, 78 insertions(+), 10 deletions(-)
diff --git
INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 10
convention.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 25 -
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915
clock and dividers
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
v2: Fixed Jani's review comments.
Signed-off-by: Uma Shankar
...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 40 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 41 ++
2 files changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/i915
register.
3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
code. Fixed the macros to get proper port offsets.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan
type and
calls appropriate core pll disable function.
v2: Fixed Jani's review comments.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2
From: Shashank Sharma shashank.sha...@intel.com
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar
: Program Tx Rx and Dphy clocks
drm/i915/bxt: DSI disable and post-disable
drm/i915/bxt: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (2):
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions
(0x1b 24)
v2: Fixed Jani's review comment.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 27 ---
drivers/gpu/drm/i915/intel_drv.h
in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
comments.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35
From: Shashank Sharma shashank.sha...@intel.com
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar uma.shan
Fixed dsi crtc state. Updated the get config function
and handled the DSI and DDI encoder cases.
BXT DSI have to be handled differently from rest of the encoders.
Reading the port control register to determine if DSI is enabled.
Generalizing it for all existing platforms.
Signed-off-by: Uma
For BXT DSI, vtotal, vactive, hactive registers are different.
Making changes to intel_crtc_mode_get() and get_pipe_timings(),
to read the correct registers for BXT DSI.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
---
transcoder. Hence this needs special
handling for BXT DSI.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h |3 +++
drivers/gpu/drm/i915/intel_display.c | 27 +++
2 files changed, 26 insertions(+), 4 deletions(-)
diff
design.
Uma Shankar (3):
drm/i915/: DSI mode setting fix
drm/i915/bxt: Get pipe timing for BXT DSI
drm/i915/bxt: Fixed dsi enc disable and blank at bootup
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 161 +++---
2 files
Added INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
--
ER
v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/
emoved the GET_DSI_PORT_CTRL Macro for consistency with earlier
implementations as per Jani's suggestion.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 36 +-
TIL_PIN_MODE_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
v3: Split the backight PWM frequency programming into separate patch,
in cases BIOS doesn't initializes it.
Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
Signed-off-by: Sunil Kamath <sunil.kam..
In some cases, BIOS doesn't initializes DSI panel.DSI and
backlight registers are thereby not initialized. Programming
the same in driver backlight setup.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h|3 +++
drivers/gpu/drm/i915/intel_p
Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/inte
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
v3: Fixed Jani's review comments
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c |8 +---
1 file chan
justed as per convention.
v3: Removed a redundant change wrt code comment.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22
drivers/gpu/drm/i915/intel_dsi.c |2 +
in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 20 +++-
1 file c
ations as per Jani's suggestion.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c
s for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 62 ++
drivers/gpu/drm/i91
ashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h |7 ++
drivers/gpu/drm/i915/intel_dsi.c | 165 ++
2 files changed, 119 insertions(+), 53 deletions(-)
diff --git a/dr
From: Shashank Sharma <shashank.sha...@intel.com>
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by:
: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (3):
drm/i915/bxt: Program Backlight PWM frequency
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
drm/i915: Added BXT DSI backlight support
atform type and
calls appropriate core pll disable function.
v2: Fixed Jani's review comments.
v3: Rebased on latest drm-nightly branch.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/inte
tected DDI code paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c |7 +--
drivers/gpu/drm/i915/intel_display.c | 21 +++-
tected DDI code paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 83
Jani's review comment wrt util pin enable
Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
Signed-off-by: Sunil Kamath <sunil.kam...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h| 28
drivers/gpu/drm/
off-by: Vandana Kannan <vandana.kan...@intel.com>
Signed-off-by: Sunil Kamath <sunil.kam...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h| 28 +
drivers/gpu/drm/i915/intel_drv.h |2 +
d
ed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 21 -
drivers/gpu/drm/i915/intel_display.c | 21 +++-
s for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
v4: Addressed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 62 +++
in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
v4: Making backlight calls generic as per Jani's suggestion.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/g
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_edid.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drive
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_edid.c | 58
1 file changed, 58 insertions(+)
diff --git a/drive
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
inclu
Attach HDR metadata property to connector object.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 41267ff..d8b53d0
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_at
.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_edid.c | 53 +
drivers/video/hdmi.c | 138
include/drm/drm_edid.h |4 ++
include/linux/hdmi.h | 21 +++
4 files changed, 216 inse
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_connector.c |7 +++
include/drm/drm_connector.h | 11 +++
i
,
generic property design and infoframe handling. This cannot get merged as of
now without
the userspace support in place. This series is not yet tested.
Uma Shankar (9):
drm: Add HDR source metadata property
drm: Add CEA extended tag blocks and HDR bitfield macros
drm: Parse HDR metadata info
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h |2 ++
2 files changed, 26 inse
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c
Add plane gamma as blob property and size as a
range property.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c|8
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c | 14 ++
inclu
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_plane.c | 48 ++
include/drm/drm_color_mgmt.h |5 +
2
Add Plane Degamma as a blob property and plane
degamma size as a range property.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c| 12
drivers/gpu/drm/drm_atomic_helper.c |6 ++
drivers/gpu/drm/drm_mode_config.c
will re-send the series with a hardware specific
implementation along with IGT tests for plane color.
Uma Shankar (6):
drm: Add Plane Degamma properties
drm: Add Plane CTM property
drm: Add Plane Gamma properties
drm: Define helper function for plane color enabling
drm: Define helper
Add a blob property for plane CSC usage.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c |7 +++
include/drm/drm_mode_config.h
Define a helper function to set legacy gamma table
size for planes.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_color_mgmt.c | 41 ++
include/drm/drm_color_mgmt.h |3 +++
include/drm/drm_plane.h |4 +
Enable and initilaize plane color features.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h |8
drivers/gpu/drm/i915/intel_color.c | 14 ++
drivers/gpu/drm/i915/intel_display.c |4
drivers/gpu/drm/i915/intel
Add plane gamma as blob property and size as a
range property.
v2: Rebase
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c|8
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c
Add a blob property for plane CSC usage.
v2: Rebase
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c |7 +++
include/drm/drm_mode_co
Enable and initialize plane color features.
v2: Rebase and some cleanup
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h| 10 ++
drivers/gpu/drm/i915/intel_color.c | 12
drivers/gpu/drm/i915/intel_drv.h |9 ++
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_plane.c | 45 ++
include/drm/drm_color_mgmt.h
Implement Plane Gamma feature for BDW and Gen9 platforms.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c |5 ++-
drivers/gpu/drm/i915/i915_reg.h | 24 ++
drivers/gpu/drm/i915/intel_color.c
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_atomic_plane.c |4
drivers/gpu/drm/i915/intel_color.c|8
drive
Add Plane Degamma as a blob property and plane
degamma size as a range property.
v2: Rebase
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_atomic.c| 12
drivers/gpu/drm/drm_atomic_helper.c |6 ++
drivers/gpu/drm/drm_mode_co
look ok.
Based on community feedback on interfaces, we will implement IGT tests to
validate
plane color features. This is un-tested currently.
v2: Dropped legacy gamma table for plane as suggested by Maarten. Added
Gen9/BDW plane
gamma feature and rebase on tot.
Uma Shankar (7):
drm: Add
This
patch fixes the same by properly scaling down all the full
range co-efficients with limited range scaling factor.
v2: Fixed Ville's review comments.
Signed-off-by: Johnson Lin <johnson@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/d
son Lin <johnson@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/
This
patch fixes the same by properly scaling down all the full
range co-efficients with limited range scaling factor.
v2: Fixed Ville's review comments.
v3: Changed input to const and used correct data types as
suggested by Ville
Signed-off-by: Johnson Lin <johnson@intel.com>
Sign
This
patch fixes the same by properly scaling down all the full
range co-efficients with limited range scaling factor.
Signed-off-by: Johnson Lin <johnson@intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 16
1
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 5
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 25
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 9 +
drivers/gpu/drm/drm_atomic.c| 13 +
drivers/gpu/drm/drm_atomic_helper.c | 6 ++
drivers/gpu/drm/drm_plane.c
umentation as suggested by Daniel, Vetter.
Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov.
v4: Rebase
Uma Shankar (8):
drm: Add Enhanced Gamma LUT precision structure
drm: Add Plane Degamma properties
drm: Add Plane CTM property
drm: Add Plane Gamma properties
d
.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 19 +++
include/uapi/drm/drm_mode.h | 15 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 6153cbd..cd71fd0 100644
--- a/drivers
documentation as suggested by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 6 ++
drivers/gpu/drm/drm_atomic.c| 9 +
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
drivers/gpu/drm/drm_plane.c | 23
by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c | 4
drivers/gpu/drm/drm_plane.c | 12
include/drm/drm_plane.h
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 42
"Colorspace" "BT2020_rgb"
Please provide comments on this current approach. This is just an RFC
to get some feedback. Will refine the series based on inputs and
feedback.
Uma Shankar (3):
drm: Add colorspace property
drm/i915: Attach colorspace property and enable modeset
drm/
This patch adds a colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c| 4
drivers/gpu/drm/drm_connector.c | 31
Based on colorspace property value create an infoframe
with appropriate colorspace. This can be used to send an
infoframe packet with proper colorspace value set which
will help to enable wider color gamut like BT2020 on sink.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
2 files changed
.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_plane.c | 19 +++
include/uapi/drm/drm_mode.h | 15 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index a5d1fc7..e706da6
documentation as suggested by Daniel, Vetter.
Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov.
Uma Shankar (8):
drm: Add Enhanced Gamma LUT precision structure
drm: Add Plane Degamma properties
drm: Add Plane CTM property
drm: Add Plane Gamma properties
drm: Define helper
by Daniel, Vetter.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
drivers/gpu/drm/drm_plane.c | 12
include/drm/drm_p
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/drm_plane.c
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