[Intel-gfx] [PATCH 1/2] drm/i915/bxt: Universal plane pixel format support

From: vandita kulkarni <vandita.kulka...@intel.com> This patch adds support for RGB formats on sprites for BXT (as per Bspec) as we have Universal planes This patch also adds support for AYUV format on primary and sprites. Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com>

[Intel-gfx] [PATCH 0/2] Universal plane pixel format support

From: vandita kulkarni <vandita.kulka...@intel.com> On bxt (as per bspec) all the planes support same set of pixel formats. The below patch adds support for all RGB formats on sprites. BXT supports AYUV format hence adding the support in drm and i915 driver. These patches have been

[Intel-gfx] [PATCH 2/2] drm: Add AYUV format support in get_plane_cpp

From: vandita kulkarni <vandita.kulka...@intel.com> This patch adds the missing DRM_FORMAT_AYUV case in get_plane_cpp function. AYUV has 4 bytes per pixel composition, that is 8 bit samples for each component with 8 bit alpha blend. Signed-off-by: vandita kulkarni <vandita.kulka...@

[Intel-gfx] [PATCH 6/9] drm/i915/skl: Drop alpha in non ARGB formats

From: vandita kulkarni <vandita.kulka...@intel.com> This patch drops alpha by default if the selected format is not ARG. This is to make sure that we drop alpha on non-ARGB formats and not fail the ATOMIC IOCTL. Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- dri

[Intel-gfx] [PATCH 7/9] drm/i915: Support blend func on primary

From: vandita kulkarni <vandita.kulka...@intel.com> Check blend state set by blend properties and set alpha blending accordingly. Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 12 +++- 1 file changed, 11 insertions(+)

[Intel-gfx] [PATCH 0/9] Support blending modes of display planes

From: vandita kulkarni <vandita.kulka...@intel.com> The below patches support plane and pixel blending by adding two properties blend_func and blend_color. As per Damien's initial patches, this design based on OpenGL's blend equations is suggested by Ville. All the below patches are

[Intel-gfx] [PATCH 2/9] drm/i915/skl: Add blend_func to SKL/BXT sprite planes

mien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 106 --- drivers/gpu/drm/i915/intel_drv.h | 11 +++- drivers/gpu/drm/i915/intel_sprite.c | 4 ++ 3 files changed, 112 insertio

[Intel-gfx] [PATCH 1/9] drm: Introduce the blend-func property

blend equation, separate rgb/alpha blend factors, blend color. V2: Added the belnd func property support in get property. Suggested-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Vandita Kulkarni <vandi

[Intel-gfx] [PATCH 3/9] drm: Introduce DRM_MODE_COLOR()

From: Damien Lespiau In the hope of expressing colors in the KMS API in a consitant want, let's introduce a ARGB 16161616 color and a few convinience macros around it. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_sprite.c |

[Intel-gfx] [PATCH 8/9] drm/i915/skl: Support blend color on primary

From: vandita kulkarni <vandita.kulka...@intel.com> Set the global alpha value for primary plane in the PLANE_KEYMAX register, to enable which set plane alpha enable bit in the PLANE_KEYMSK register. On bxt only 8 bit alpha will be considered from the PLANE_KEYMAX register. Sign

[Intel-gfx] [PATCH 5/9] drm/i915/skl: Add support for blending modes

From: Damien Lespiau This patch adds support for blending modes involving color. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 28 drivers/gpu/drm/i915/intel_drv.h | 1 +

[Intel-gfx] [PATCH 9/9] drm/i915/skl: Separate out disable plane alpha

From: vandita kulkarni <vandita.kulka...@intel.com> Separate out plane alpha disable functionality from per pixel drop_alpha blend function and add another blend function case for disabling plane alpha. Fix the state info ,so that premultiplied alpha doesn't always become false when drop

[Intel-gfx] [PATCH 4/9] drm: Add an blend_color property

From: Damien Lespiau <damien.lesp...@intel.com> Add blend color property and update the documentation for the same V2: Add blend color support in get property. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kul

[Intel-gfx] [PATCHv2 4/5] drm: Add an blend_color property

From: Damien Lespiau <damien.lesp...@intel.com> Add blend color property and update the documentation for the same V2: Add blend color support in get property. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kul

[Intel-gfx] [PATCHv2 1/5] drm: Introduce the blend-func property

blend equation, separate rgb/alpha blend factors, blend color. V2: Added the belnd func property support in get property. Suggested-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Vandita Kulkarni <vandi

[Intel-gfx] [PATCHv2 0/5] Support blending modes of display planes

From: vandita kulkarni <vandita.kulka...@intel.com> The below patches support plane and pixel blending by adding two properties blend_func and blend_color. As per Damien's initial patches, this design based on OpenGL's blend equations is suggested by Ville. All the below patches are

[Intel-gfx] [PATCHv2 2/5] drm/i915/skl: Add blend_func to SKL/BXT sprite planes

cursor planes. fix an issue where the previous value was not retained, change the logic to do so. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- drivers/gpu/drm/i915/int

[Intel-gfx] [PATCHv2 5/5] drm/i915/skl: Add support for blending modes

alpha. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_display.c | 47 drivers/gpu/drm/i915/in

[Intel-gfx] [PATCHv2 3/5] drm: Introduce DRM_MODE_COLOR()

From: Damien Lespiau In the hope of expressing colors in the KMS API in a consitant want, let's introduce a ARGB 16161616 color and a few convinience macros around it. Signed-off-by: Damien Lespiau --- include/uapi/drm/drm_mode.h | 34

[Intel-gfx] [PATCHv2 1/5] drm: Introduce the blend-func property

blend equation, separate rgb/alpha blend factors, blend color. V2: Added the belnd func property support in get property. Suggested-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Vandita Kulkarni <vandi

[Intel-gfx] [PATCHv2 0/5] Support blending modes of display planes

From: vandita kulkarni <vandita.kulka...@intel.com> The below patches support plane and pixel blending by adding two properties blend_func and blend_color. As per Damien's initial patches, this design based on OpenGL's blend equations is suggested by Ville. All the below patches are

[Intel-gfx] [PATCHv2 4/5] drm: Add an blend_color property

From: Damien Lespiau <damien.lesp...@intel.com> Add blend color property and update the documentation for the same V2: Add blend color support in get property. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kul

[Intel-gfx] [PATCHv2 3/5] drm: Introduce DRM_MODE_COLOR()

From: Damien Lespiau In the hope of expressing colors in the KMS API in a consitant want, let's introduce a ARGB 16161616 color and a few convinience macros around it. Signed-off-by: Damien Lespiau --- include/uapi/drm/drm_mode.h | 34

[Intel-gfx] [PATCHv2 2/5] drm/i915/skl: Add blend_func to SKL/BXT sprite planes

cursor planes. fix an issue where the previous value was not retained, change the logic to do so. Signed-off-by: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: vandita kulkarni <vandita.kulka...@intel.com> --- drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH] drm/i915: Enable hw workaround to bypass alpha

Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_reg.h | 8 drivers/gpu/drm/i915/intel_display.c | 12 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..6e59bfe 100644 --- a/drivers

[Intel-gfx] [v2] drm/i915: Enable hw workaround to bypass alpha

: Fix patchwork checkpatch warnings. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_reg.h | 8 drivers/gpu/drm/i915/intel_display.c | 12 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi

From: Madhav Chauhan This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Used during the atomic modeset. v2: use intel_dsi_bitrate instead of intel_dsi->pclk Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI

Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_display.c | 4 +++- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fc7e3b0..ddbba92 100644

[Intel-gfx] [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi

The same pll manager functions can be used to enable dpll for mipi. Hence enabling the IO power and esc clock as part of pre pll enable call. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 0/3] ICL DSI PLL enable

power-on related patches present at https://github.com/madhavchauhan/Intel-DSI-Driver Madhav Chauhan (2): drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Add get_config functionality for dsi Vandita Kulkarni (1): drm/i915/icl: Use the same pll functions for dsi drivers/gpu/drm/i915

[Intel-gfx] [PATCH 5/6] drm/i915/icl: Ungate DSI clocks

From: Madhav Chauhan Ungate the clocks on the selected port. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 6/6] drm/i915/icl: Update port clock in compute config

For DSI 8X clock is AFE clock which is is 5 times port clock. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 80382fb..2812129 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 2/6] drm/i915/icl: Use the same pll functions for dsi

The same pll manager functions can be used to enable dpll for mipi. Hence enabling the IO power and esc clock as part of pre pll enable call. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 4/6] drm/i915/icl: Gate clocks for DSI

From: Madhav Chauhan As per BSPEC, depending on the DSI transcoder being used, DDI clock for the associated port should be gated. This patch does the same. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 20 1 file

[Intel-gfx] [PATCH 1/6] drm/i915/icl: Calculate DPLL params for DSI

by 5 Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_display.c | 4 +++- drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/6] drm/i915/icl: Get port clock from pll.

Use the same method to get port clock like other encoders. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 10 -- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dsi.h | 4 3 files changed, 13 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 0/6] ICL DSI PLL enable

://people.freedesktop.org/~jani/drm and the patches are rebased on this. Madhav Chauhan (3): drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Gate clocks for DSI drm/i915/icl: Ungate DSI clocks Vandita Kulkarni (3): drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Get

[Intel-gfx] [RFC 3/3] drm/i915/icl: Calculate DPLL params for DSI

From: Madhav Chauhan This patch calculate various DPLL dividers and parameters for DSI encoder and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock. v2: Extend haswell_crtc_compute_clock() for Gen11 DSI v3: Rebase Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni

[Intel-gfx] [RFC 1/3] drm/i915/icl: Restructure ICL DPLL enable functionality

From: Madhav Chauhan In Gen11, DPLL 0 and 1 are shared between DDI and DSI. Most of the steps for enabling DPLL are common across DDI and DSI. This patch makes icl_dpll_enable() generic which will be used by all the encoders. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni

[Intel-gfx] [RFC 0/3] Enable ICL DSI PLL

Gen11/ICL DSI has to choose one of the free available DPLL which can also be tied to DDI A/B combo phy ports. In legacy platforms that was not the case as DSI had separate/exclusive PLLs. ICL DPLL enable/disable steps are 80% common if DPLL is tied to DDI interface (HDMI/DP) or DSI. If DSI

[Intel-gfx] [RFC 2/3] drm/i915/icl: Enable Gen11 DSI PLL

From: Madhav Chauhan This patch implements steps specific to DSI for enabling PLL. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 41 - 1 file changed, 40 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi

Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 2 files changed, 4

[Intel-gfx] [v3 1/2] drm/i915/icl: Ungate ddi clocks before IO enable

IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Signed-off-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/icl_dsi.c | 6 ++ 1

[Intel-gfx] [PATCH 0/3] Fix mipi dsi pipe_config mismatch for icl

This is series fixes the WARN_ON that we see due to pipe_config mismatch on mipi dsi for icl. Only DSI0 trancoder regs are read even in case of dual link mode as the values programmed for DSI0 and DSI1 transcoder registers are same. Vandita Kulkarni (3): drm/i915: Fix pipe config timing

[Intel-gfx] [PATCH 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

Read back the pixel fomrat register and get the bpp. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 28 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index db6bc3d..69cd6b2 100644

[Intel-gfx] [PATCH 1/3] drm/i915: Fix pipe config timing mismatch warnings

Mipi dsi programs the transcoder timings as part of encoder enable sequence, with dual link or single link in consideration. Hence add get transcoder timings as part of the encoder's get_config function. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 51

[Intel-gfx] [PATCH 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get from the VBT is halved. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index

[Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence

Re-enable clock gating of DDI clocks. Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c

[Intel-gfx] [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated

IO enable sequencing needs ddi clocks enabled. These clocks will be gated at the later point in the enable sequence. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm

[Intel-gfx] [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable

IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (uma) Signed-off-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/icl_dsi.c | 7 +++ 1 file changed, 7 insertions(+) diff

[Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi

Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 2 files changed, 4

[Intel-gfx] [PATCH 2/2] drm/i915: Add intel_dsi properties support for icl

Support dsi properties on icl Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 1e240ad665b5..cd2e1b73acad 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c

[Intel-gfx] [PATCH 1/2] drm/i915: Move intel_add_dsi_properties to intel_dsi

Since intel_add_dsi_properties will be used by other platforms too move it out of platform specific file. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_dsi.c | 32 drivers/gpu/drm/i915/intel_dsi.h | 3 +++ drivers/gpu/drm/i915/vlv_dsi.c | 42

[Intel-gfx] [v3 1/4] drm/i915: Fix the pipe state timing mismatch warnings

Adjust the get transcoder timings for mipi dsi as per the set timing calculations. v2: Use the existing intel_get_pipe_timings and do the dsi specific adjustments in the encoder get_config hook.(Ville, Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 29

[Intel-gfx] [v3 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp

Move bdw_get_pipemisc_bpp alongside bdw_set_pipemisc Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_display.c | 22 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/vlv_dsi.c | 22 -- 3 files changed, 23

[Intel-gfx] [v3 4/4] drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get from the VBT is halved. v2: Simplify the calculation (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915

[Intel-gfx] [v3 3/4] drm/i915: Fix pipe config mismatch for bpp, output format

Read back the pixel fomrat register and get the bpp. v2: Read the PIPE_MISC register (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 45fe69c

[Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

Read back the pixel fomrat register and get the bpp. v2: Read the PIPE_MISC register (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 3 +++ drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/vlv_dsi.c | 2 +- 3 files changed, 5 insertions(+), 1

[Intel-gfx] [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings

Adjust the get transcoder timings for mipi dsi as per the set timing calculations. v2: Use the existing intel_get_pipe_timings and do the dsi specific adjustments in the encoder get_config hook.(Ville, Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 29

[Intel-gfx] [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get from the VBT is halved. v2: Simplify the calculation (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915

[Intel-gfx] [v4 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp

Move bdw_get_pipemisc_bpp alongside bdw_set_pipemisc Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_display.c | 22 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/vlv_dsi.c | 22 -- 3 files changed, 23

[Intel-gfx] [v4 1/4] drm/i915: Fix the pipe state timing mismatch warnings

Adjust the get transcoder timings for mipi dsi as per the set timing calculations. v2: Use the existing intel_get_pipe_timings and do the dsi specific adjustments in the encoder get_config hook.(Ville, Jani) v3: Exclude VBLANK and HBLANK registers for dsi transcoder. Signed-off-by: Vandita

[Intel-gfx] [v4 4/4] drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get from the VBT is halved. v2: Simplify the calculation (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915

[Intel-gfx] [v4 3/4] drm/i915: Fix pipe config mismatch for bpp, output format

Read back the pixel fomrat register and get the bpp. v2: Read the PIPE_MISC register (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 45fe69c

[Intel-gfx] [v5 3/4] drm/i915: Fix pipe config mismatch for bpp, output format

Read back the pixel fomrat register and get the bpp. v2: Read the PIPE_MISC register (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 45fe69c

[Intel-gfx] [v5 4/4] drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get from the VBT is halved. v2: Simplify the calculation (Jani). Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915

[Intel-gfx] [v5 1/4] drm/i915: Fix the pipe state timing mismatch warnings

conditional logic. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 29 + drivers/gpu/drm/i915/intel_display.c | 22 -- 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b

[Intel-gfx] [v5 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp

Move bdw_get_pipemisc_bpp alongside bdw_set_pipemisc Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_display.c | 22 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/vlv_dsi.c | 22 -- 3 files changed, 23

[Intel-gfx] [V2] drm/i915: Add icl mipi dsi properties

Add scaling and panel orientation properties for icl mipi dsi. v2: Add platform specific function (Ville) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 30 ++ drivers/gpu/drm/i915/display/vlv_dsi.c | 4 ++-- 2 files changed, 32 insertions

[Intel-gfx] [V3] drm/i915: Add icl mipi dsi properties

Add scaling and panel orientation properties for icl mipi dsi. v2: Add platform specific function (Ville) v3: Remove redundant check and update scaler call (Jani, Ville) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

Rest of the latency programming remains same as that of ICL. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index

[Intel-gfx] [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register

Program vblank register for mipi dsi in video mode on TGL. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index b8673debf932

[Intel-gfx] [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping

No need to keep it on till IO enabling. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index d1c50a4186f0

[Intel-gfx] [PATCH 0/4] Support mipi dsi video mode on TGL

This series doesn't include the patch to add dsi init in setup_outputs. Waiting for the platform enablemnet patches to be merged. Vandita Kulkarni (4): drm/i915/tgl/dsi: Program TRANS_VBLANK register drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl drm/i915/tgl/dsi: Do not override TA_SURE

[Intel-gfx] [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE

Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or below on TGL. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register

Program vblank register for mipi dsi in video mode on TGL. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index a42348be0438

[Intel-gfx] [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode

Blanking packet bit will control whether the transcoder allows the link to enter the LP state during BLLP regions (assuming there is enough time), or whether it will keep the link in the HS state with a Blanking Packet Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c

[Intel-gfx] [v2 2/6] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

Latency programming remains same as that of ICL and setting latency otimization for PCS_DW1 lanes is same as that of EHL, hence extending it to TGL. Signed-off-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[Intel-gfx] [v2 3/6] drm/i915/tgl/dsi: Do not override TA_SURE

Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or below on TGL. Signed-off-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git

[Intel-gfx] [v2 0/6] Support mipi dsi video mode on TGL

Most of the sequence remains as same as that of ICL. This series includes the changes needed for TGL. Vandita Kulkarni (6): drm/i915/tgl/dsi: Program TRANS_VBLANK register drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl drm/i915/tgl/dsi: Do not override TA_SURE drm/i915/tgl/dsi: Gate

[Intel-gfx] [v2 4/6] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping

For TGL, there is no need to keep DDI clock on till IO enabling for mipi dsi. Signed-off-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL

Most of the functions and mipi dsi sequence remains same as of ICL for TGL. Hence extending the support to TGL. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b

[Intel-gfx] [RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi cmd mode.

In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 62 + 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915

[Intel-gfx] [RFC-v2 1/9] drm/i915/dsi: Define command mode registers

Adding all the register definitions needed for mipi dsi command mode. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_reg.h | 78 + 1 file changed, 70 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [RFC-v2 5/9] drm/i915/dsi: Add check for periodic command mode

If the GOP has programmed periodic command mode, we need to disable that which would need a deconfigure and configure sequence. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags

Adding TE flags and periodic command mode flags as part of private flags to indicate what TE interrupts we would be getting instead of vblanks in case of mipi dsi command mode. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++ 1 file changed, 6

[Intel-gfx] [RFC-v2 6/9] drm/i915/dsi: Use private flags to indicate TE in cmd mode

On dsi cmd mode we do not receive vblanks instead we would get TE and these flags indicate TE is expected on which port. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [RFC-v2 9/9] drm/i915/dsi: Initiate fame request in cmd mode

In TE Gate mode, on every flip we need to set the frame update request bit. After this bit is set transcoder hardware will automatically send the frame data to the panel when it receives the TE event. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 22

[Intel-gfx] [RFC-v2 3/9] drm/i915/dsi: Add vblank calculation for command mode

Transcoder timing calculation differ for command mode. v2: Use is_vid_mode, and use same I915_WRITE (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 39 +- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for cmd mode

We need to configure TE interrupt in two places. Port interrupt and DSI interrupt mask registers. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 58 +++-- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [RFC-v2 0/9] Add support for mipi dsi cmd mode

Fixed the comments on version1 RFC, basically fixing the challenge on getting access to mipi dsi attributes like is command mode enabled, and what should be the port for reading TE and doing a frame update. Thanks to Jani and Ville for their inputs on this. Vandita Kulkarni (9): drm/i915/dsi

[Intel-gfx] [PATCH] drm/i915/tgl: Do not read the transcoder register for mipi dsi

As per the Bspec the port mapping is fixed for mipi dsi Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 27 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915

[Intel-gfx] [RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode.

Configure the transcoder to operate in TE GATE command mode and take TE events from GPIO. Also disable the periodic command mode, that GOP would have programmed. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++ 1 file changed, 36

[Intel-gfx] [PATCH] drm/i915: Fix WARN_ON condition for cursor plane ddb allocation

In some cases min_ddb_alloc can be U16_MAX, exclude it from the WARN_ON. Fixes: 10a7e07b68b9 ("drm/i915: Make sure cursor has enough ddb for the selected wm level") Suggested-by: Ville Syrjälä Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file

[Intel-gfx] [PATCH] drm/i915: Fix WARN_ON condition for cursor plane ddb allocation

t;) Suggested-by: Ville Syrjälä Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ccbbdf4a6aab..7cdca0

[Intel-gfx] [RFC 1/1] drm/i915/dsi: Add dsi_state in crtc_state

This patch add dsi_state which provides dsi operation mode and the link mode. These are needed in order to check if they were differently configured by GOP. In present case the GOP enables dsi in periodic update mode, whereas we need to enable it in TE_GATE command mode. In which case a

[Intel-gfx] [RFC 0/1] Add dsi_state in crtc_state

/ Vandita Kulkarni (1): drm/i915/dsi: Add dsi_state in crtc_state drivers/gpu/drm/i915/display/icl_dsi.c| 39 +++ .../drm/i915/display/intel_display_types.h| 12 ++ 2 files changed, 51 insertions(+) -- 2.21.0.5.gaeb582a

[Intel-gfx] [PATCH] drm/i915/dsi: Do not read the transcoder register.

As per the Bspec, port mapping is fixed for mipi dsi. v2: Reuse the existing function (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [V3 3/8] drm/i915/dsi: Add cmd mode flags in display mode private flags

Adding TE flags and periodic command mode flags as part of private flags to indicate what TE interrupts we would be getting instead of vblanks in case of mipi dsi command mode. v2: Add TE flag description (Jani) Reviewed-by: Jani Nikula Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915

[Intel-gfx] [V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. v2: Pass only relevant masked bits to the handler (Jani) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 64 + 1 file changed, 64 insertions(+) diff --git

  1   2   3   >