[Intel-gfx] [PATCH 00/40] CHV stuff mostly

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com I was slaving over my bsw for most of the past week and this is the result. It should really be split up into several series, but no time now when vacation is calling. So I figured that I'll just post the entire pile and disappear. The whole lot

[Intel-gfx] [PATCH 01/40] drm/i915: Try to populate mem_freq for chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com mem_freq is needed to decode the GPU freq opcodes. FIXME: Punit reg seems to contain garbage so this isn't right Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 18 ++ 1 file

[Intel-gfx] [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com No need to re-read the hardware rps fuses when we already have all the values tucked away in dev_priv-rps. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-

[Intel-gfx] [PATCH 06/40] drm/i915: Add cdclk change support for chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Looks like the Punit is supposed to support the 400MHz cdclk directly on chv, so we don't need the vlv tricks. FIXME: Punit doesn't seem ready for this yet on current hw Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV was forgotten the intel_{dp,hdmi}_prepare() were introduced (or the chv patches were still in flight?). Call these when enabling the ports. Things tend to work much better when we actually write something to the port registers :)

[Intel-gfx] [PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave()

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com init_clock_gating() is too late to read out the mem_freq. We already want to print out the GPU MHz numbers before it's called. Move the mem_freq setup to init_gt_powersave(). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 08/40] drm/i915: Leave DPLL ref clocks on

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com We enable the DPLL refclock already when bringing up the cmnlane power well, so also leave it on when otherwise disabling the DPLL. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1

[Intel-gfx] [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV wants even rps opcodes so make sure the min/max/rpe values are also even. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 8 drivers/gpu/drm/i915/intel_pm.c | 19

[Intel-gfx] [PATCH 13/40] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The register can house two different swing marging/deemph settings at once. However only one gets used based on some other bits. Make sure we set those bits correctly to make the hardware use the settings we provided. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV display PHY registes have two swing margin/deemph settings. Make it clear which ones we're using. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 8 ++-- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 16/40] drm/i915: Add chv_power_wells[]

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add chv_power_wells[] so we can start to build up the power well support for chv. Just the always on well there initialy. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 11 +++ 1 file

[Intel-gfx] [PATCH 22/40] drm/i915: Add chv port D TX wells

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add the TX wells for port D. The Punit subsystem numbers are a total guess at this time. Also I'm not sure these even exist. Certainly the Punit in current hardware doesn't deal with these. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 18/40] drm/i915: Kill intel_reset_dpio()

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Both VLV and CHV handle the cmnreset stuff in the power well code now, so intel_reset_dpio() is no longer needed. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 31

[Intel-gfx] [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Just an attempt to frob these bits. Apparently we should not need to touch them (apart from maybe making sure the override is disabled so that the hardware automagically does the right thing). Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 09/40] drm/i915: Split chv_update_pll() apart

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Split chv_update_pll() into two parts ala: commit bdd4b6a655749970cc632aafc5fd596c07b60b1c Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Thu Apr 24 23:55:11 2014 +0200 drm/i915: Extract vlv_prepare_pll Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

2014-06-27 Thread ville . syrjala
From: Zhenyu Wang zhen...@linux.intel.com Signed-off-by: Zhenyu Wang zhen...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 50 - drivers/gpu/drm/i915/intel_pm.c | 12 +- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git

[Intel-gfx] [PATCH 17/40] drm/i915: Add chv cmnlane power wells

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV has two display PHYs so there are also two cmnlane power wells. Add the approriate code to power the wells up/down. Like on VLV we do the cmnreset assert/deassert and the DPLL refclock enabling at approriate times. This code actually works

[Intel-gfx] [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The DDL registers can hold 7bit numbers. Make the most of those seven bits by adjusting the threshold where we switch between the 64 vs. 32 precision multipliers. Also we compute 'entries' to make the decision about precision, and then we

[Intel-gfx] [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Punit seems a bit WIP still. Disable cdclk changes until we have hardware where it works. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff

[Intel-gfx] [PATCH 19/40] drm/i915: Add disp2d power well for chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Not sure if it's still there since chv has per-pipe power wells. At least with current Punit this doesn't work. Also the display irq handling would need to be adjusted for pipe C. So leave the code iffed out for now. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The VLV/CHV DDL registers are uniform, and neatly enough the register offsets are sane so we can easily unify them to a single set of defines and just pass the pipe as the parameter to compute the register offset. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 21/40] drm/i915: Add chv port B and C TX wells

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add the TX wells for ports B and C just like on VLV. Again Punit doesn't seem ready (or the wells don't even exist anymore) so leave it iffed out. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c |

[Intel-gfx] [PATCH 28/40] drm/i915: Add cherryview_update_wm()

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV has a third pipe so we need to compute the watermarks for its planes. Add cherryview_update_wm() to do just that. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 77

[Intel-gfx] [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Replace the semi-funky cmnlane assert/deassert macros with something a bit more conventional. Also protect the macro arguments properly (also for PHY_POWERGOOD()). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com When switching from one pipe to another, the power sequencer of the new pipe seems to need a bit of kicking to lock into the port. Even the vdd force bit doesn't work before the power sequencer has been sufficiently kicked, so this must be done

[Intel-gfx] [PATCH 27/40] drm/i915: Split a few long debug prints

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Split some WM debug prints to multiple lines. This shouldn't hurt grappability since the important part is at the start and the rest is just repeated stuff for each pipe. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com In commit 62942ed7279d3e06dc15ae3d47665eff3b373327 Author: Jesse Barnes jbar...@virtuousgeek.org Date: Fri Jun 13 09:28:33 2014 -0700 drm/i915/vlv: disable PPGTT on early revs v3 we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so

[Intel-gfx] [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

2014-06-27 Thread ville . syrjala
From: Kenneth Graunke kenn...@whitecape.org We'll want to reuse this for a workaround. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- drivers/gpu/drm/i915/intel_ringbuffer.c | 36 - 1 file changed, 22 insertions(+), 14 deletions(-) diff --git

[Intel-gfx] [PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Allow calling the vdd off functions when vdd is already off. Makes things simpler later. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-)

[Intel-gfx] [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com It looks like frobbing the cmnreset line on pne PHY disturbs the other PHY on chv. The result is a black screen. On HDMI it's just a flash of black, but DP usually falls over and can't get back up. As a workaround set up the power domains so that

[Intel-gfx] [PATCH 31/40] drm/i916: Init chv workarounds at render ring init

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com My bsw is an unhappy camper if we delay the workaround init until init_clock_gating(). Move a bunch of it to the render ring init. FIXME: need to do this for all platforms since some of the registers also get clobbered at reset. Just need

[Intel-gfx] [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV supports DP training pattern 3. Add the required stuff. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 18 ++ 2 files changed, 16

[Intel-gfx] [PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits on chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Clear the override bits to make sure the hardware maanages the TX FIFO reset master on its own. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 20 +++-

[Intel-gfx] [PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The panel power sequencer locks into the port once used. We need to keep track wich power sequencers are locked to which ports. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 172

[Intel-gfx] [PATCH 20/40] drm/i915: Add per-pipe power wells for chv

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV has a power well for each pipe. Add the code to deal with them. The Punit in current hardware doesn't seem ready for this yet, so leave it iffed out. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com When we pick a new power sequencer for the port but we're not doing a full modeset, the power sequencer may have locked on to another port. So kick it a bit to make sure it controls the port we want. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 10/40] drm/i915: Call encoder-post_disable() in intel_sanitize_encoder()

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com VLV and CHV disable the DP port only in the .post_disable() hook, so we need to make intel_sanitize_encoder() call that when it's trying to disable encoders without an active pipes. My bsw actaully hits this when an external display is connected.

[Intel-gfx] [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add defines for all the watermark registers on modernish gmch platforms. VLV has increased the number of bits available for certain watermaks so expand the masks appropriately. Also vlv and chv have added some extra FW registers. Not sure what

[Intel-gfx] [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

2014-06-27 Thread ville . syrjala
From: Kenneth Graunke kenn...@whitecape.org On Broadwell, any PIPE_CONTROL with the State Cache Invalidate bit set must be preceded by a PIPE_CONTROL with the CS Stall bit set. Documented on the BSpec 3D workarounds page. Signed-off-by: Kenneth Graunke kenn...@whitecape.org [vsyrjala: add chv

[Intel-gfx] [PATCH 35/40] drm/i915: Fix vdd locking

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Currently we do all kinds vdd frobbing from both the modeset and -detect. -detect isn't protected by the connection_mutex as the current locking stuff seems to expect. Switch it all over the mode_config.mutex instead since we hold that in both

[Intel-gfx] [PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port

2014-06-27 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com In case the pipe's power sequencer has been locked to another port, we need to kick it to make it unstuck. Otherwise it will prevent the port from starting up even if it's a regular DP port and not eDP. We can't use the regular panel power

[Intel-gfx] [PATCH] drm/i915: Add a bit of locking to intel_dp_hpd_pulse()

2014-07-30 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com -hpd_pulse() is called from a workqueue via an interrupt so it happens asynchronously with modesets. Grab the connection_mutex in intel_dp_hpd_pulse() to avoid disturbing on angoing modeset with parallel hpd processing. On my IVB turning off the

[Intel-gfx] [PATCH v2 26/40] drm/i915: Parametrize VLV_DDL registers

2014-07-31 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The VLV/CHV DDL registers are uniform, and neatly enough the register offsets are sane so we can easily unify them to a single set of defines and just pass the pipe as the parameter to compute the register offset. Note that we now fill out the

[Intel-gfx] [PATCH v2 25/40] drm/i915: Fill out the FWx watermark register defines

2014-08-01 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add defines for all the watermark registers on modernish gmch platforms. VLV has increased the number of bits available for certain watermaks so expand the masks appropriately. Also vlv and chv have added some extra FW registers. Not sure what

[Intel-gfx] [PATCH v2 28/40] drm/i915: Add cherryview_update_wm()

2014-08-01 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV has a third pipe so we need to compute the watermarks for its planes. Add cherryview_update_wm() to do just that. v2: Rebase on top of Imre's cxsr changes (Paulo) Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH v2 15/40] drm/i915: Clear TX FIFO reset master override bits on chv

2014-08-01 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Clear the override bits to make sure the hardware maanages the TX FIFO reset master on its own. v2: Squash with the earlier attempt at forcing the override bits Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- Note to maintainer:

[Intel-gfx] [PATCH 2/2] drm/i915: Free pending page flip events at .preclose()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com If there are pending page flips when the fd gets closed those page flips may have events associated to them. When the page flip eventually completes it will queue the event to file_priv-event_list, but that may be too late and file_priv-event_list

[Intel-gfx] [PATCH 1/2] drm: Warn when leaking flip events on close

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Warn when there are events on the file_priv-event_list just before file_priv gets freed. This can occur if the driver doesn't clean up pending page flip events in -preclose(). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH v2 00/19] drm: More vblank on/off work

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com This is mostly a repost of the earlier series [1]. Most of the patches have been reviewed, but I have added quite a few new ones to the end to fix various issues. [1] http://lists.freedesktop.org/archives/dri-devel/2014-May/060518.html Ville

[Intel-gfx] [PATCH v2 01/19] drm: Always reject drm_vblank_get() after drm_vblank_off()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Make sure drm_vblank_get() never succeeds when called between drm_vblank_off() and drm_vblank_on(). Borrow a trick from the old drm_vblank_{pre,post}_modeset() functions and just bump the refcount in drm_vblank_off() and drop it in

[Intel-gfx] [PATCH 03/19] drm: Don't clear vblank timestamps when vblank interrupt is disabled

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Clearing the timestamps causes us to send zeroed timestamps to userspace if they get sent out in response to the drm_vblank_off(). It's better to send the very latest timestamp and count instead. Testcase: igt/kms_flip/modeset-vs-vblank-race

[Intel-gfx] [PATCH v2 02/19] drm/i915: Warn if drm_vblank_get() still works after drm_vblank_off()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com v2: Drop the drm_vblank_off() (Daniel) Use drm_crtc_vblank_{get,put}() Reviewed-by: Matt Roper matthew.d.ro...@intel.com Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 04/19] drm: Move drm_update_vblank_count()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Move drm_update_vblank_count() to avoid forward a declaration. No functional change. Reviewed-by: Matt Roper matthew.d.ro...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/drm_irq.c | 128

[Intel-gfx] [PATCH 05/19] drm: Have the vblank counter account for the time between vblank irq disable and drm_vblank_off()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com If the vblank irq has already been disabled (via the disable timer) when we call drm_vblank_off() sample the counter and timestamp one last time. This will make the sure that the user space visible counter will account for time between vblank irq

[Intel-gfx] [PATCH 08/19] drm: Fix deadlock between event_lock and vbl_lock/vblank_time_lock

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Currently both drm_irq.c and several drivers call drm_vblank_put() while holding event_lock. Now that drm_vblank_put() can disable the vblank interrupt directly it may need to grab vbl_lock and vblank_time_lock. That causes deadlocks since we take

[Intel-gfx] [PATCH v2 07/19] drm: Reduce the amount of dev-vblank[crtc] in the code

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Declare a local struct drm_vblank_crtc * and use that instead of having to do dig it out via 'dev-vblank[crtc]' everywhere. Performed with the following coccinelle incantation, and a few manual whitespace cleanups: @@ identifier func,member;

[Intel-gfx] [PATCH 09/19] drm: Fix race between drm_vblank_off() and drm_queue_vblank_event()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Currently it's possible that the following will happen: 1. drm_wait_vblank() calls drm_vblank_get() 2. drm_vblank_off() gets called 3. drm_wait_vblank() calls drm_queue_vblank_event() which adds the event to the queue event though vblank

[Intel-gfx] [PATCH 06/19] drm: Avoid random vblank counter jumps if the hardware counter has been reset

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com When drm_vblank_on() is called the hardware vblank counter may have been reset, so we can't trust that the old values sampled prior to drm_vblank_off() have anything to do with the new values. So update the .last count in drm_vblank_on() to make

[Intel-gfx] [PATCH v2 11/19] drm: Add dev-vblank_disable_immediate flag

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add a flag to drm_device which will cause the vblank code to bypass the disable timer and always disable the vblank interrupt immediately when the last reference is dropped. v2: Add some notes about the flag to the kernel doc Reviewed-by: Matt

[Intel-gfx] [PATCH v2 13/19] drm: Kick start vblank interrupts at drm_vblank_on()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com If the user is interested in getting accurate vblank sequence numbers all the time they may disable the vblank disable timer entirely. In that case it seems appropriate to kick start the vblank interrupts already from drm_vblank_on(). v2: Adapt

[Intel-gfx] [PATCH 14/19] drm: Don't update vblank timestamp when the counter didn't change

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com If we already have a timestamp for the current vblank counter, don't update it with a new timestmap. Small errors can creep in between two timestamp queries for the same vblank count, which could be confusing to userspace when it queries the

[Intel-gfx] [PATCH 16/19] drm: Store the vblank timestamp when adjusting the counter during disable

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com During vblank disable the code tries to guess based on the timestamps whether we just missed one vblank or not. And if so it increments the counter. However it forgets to store the new timestamp to the approriate slot in our timestamp ring buffer.

[Intel-gfx] [PATCH 12/19] drm/i915: Opt out of vblank disable timer on gen2

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Now that the vblank races are plugged, we can opt out of using the vblank disable timer and just let vblank interrupts get disabled immediately when the last reference is dropped. Gen2 is the exception since it has no hardware frame counter.

[Intel-gfx] [PATCH 15/19] drm: Update vblank-last in drm_update_vblank_count()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com We should update the last in drm_update_vblank_count() to avoid applying the diff more than once. This could occur eg. if drm_vblank_off() gets called multiple times for the crtc. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 17/19] drm/i915: Clear .last vblank count before drm_vblank_off() when sanitizing crtc state

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com We call drm_vblank_off() during crtc sanitation to make sure the software and hardware states agree. However drm_vblank_off() will try to update the vblank timestamp and sequence number which lands us in some trouble. As the pipe is disabled the

[Intel-gfx] [PATCH 19/19] drm: Fix confusing debug message in drm_update_vblank_count()

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Now that drm_update_vblank_count() can be called even when we're not about to enable the vblank interrupts we shouldn't print debug messages stating otherwise. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH igt] tests/kms_flip: Assert that vblank timestamps aren't zeroed

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The kernel might mistakenly send out a zeroed vblank timestamp when the vblank wait gets terminated early due to crtc disable. Add an assertion to catch that. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- tests/kms_flip.c | 3

[Intel-gfx] [PATCH 18/19] drm/i915: Update scanline_offset only for active crtcs

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com update_scanline_offset() in intel_sanitize_crtc() was supposed to be called only for active crtcs. But due to some underrun patches it now gets updated for all crtcs on gmch platforms. Move the update_scanline_offset() to the very beginning of

[Intel-gfx] [PATCH igt] tests: Add kms_flip_event_leak test

2014-08-06 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com kms_flip_event_leak will issue a page flip and close the file descriptor before the flip has finished. This may cause the kernel to leak the page flip event. The test itself won't actually fail but if the kernel notices the leak and WARNs piglit

[Intel-gfx] [PATCH 1/2] drm/i915: Eliminate rmw from .update_primary_plane()

2014-08-08 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Move the entire DSPCNTR register setup into the .update_primary_plane() functions. That's where it belongs anyway and it'll also help 830M which has the extra problem that plane registers reads will return the value latched at the last vblank, not

[Intel-gfx] [PATCH 2/2] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()

2014-08-08 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Make the intel_{enable,disable}_primary_hw_plane() simply call .update_primary_plane(), thus eliminating the rmw from these functions which should help the poor old 830M. Now we can also remove the .update_primary_plane() from the .crtc_enable()

[Intel-gfx] [PATCH 1/2] drm/i915: Fix locking for intel_enable_pipe_a()

2014-08-11 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com intel_enable_pipe_a() gets called with all the modeset locks already held (by drm_modeset_lock_all()), so trying to grab the same locks using another drm_modeset_acquire_ctx is going to fail miserably. Move most of the drm_modeset_acquire_ctx

[Intel-gfx] [PATCH 2/2] drm/i915: Skip load detect when intel_crtc-new_enable==true

2014-08-11 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com During suspend we turn off the crtcs, but leave the staged config in place so that we can restore the display(s) to their previous state on resume. During resume when we attempt to apply the force pipe A quirk we use the load detect mechanism.

[Intel-gfx] [PATCH] drm: Fix drm_crtc vs. drm_plane type bug in plane-reset() handling

2014-08-11 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com s/struct drm_crtc/struct drm_plane/ in drm_mode_config_reset() so that we actually dereference the correct type of structure when calling the plane-reset() hook. Imre mentioned that his VLV was crashing there on resume. I deciced to have a quick

[Intel-gfx] [PATCH] drm/i915: Make hpd debug messages less cryptic

2014-08-11 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Don't print raw numbers, use port_name() and tell the user whether it's long or short without having to figure out what the other magic number means. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [PATCH 1/4] drm/i915: Don't try to enable cursor from setplane when crtc is disabled

2014-08-12 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Make sure the cursor gets fully clipped when enabling it on a disabled crtc via setplane. This will prevent the lower level code from attempting to enable the cursor in hardware. Cc: Paulo Zanoni przan...@gmail.com Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 2/4] drm/i915: Move CURSIZE setup to i845_update_cursor()

2014-08-12 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com CURSIZE register exists on 845/865 only, so move it to i845_update_cursor(). Changes to cursor size must be done only when the cursor is disabled, so do the write just before enabling the cursor. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 0/4] drm/i915: Cursor fixes and cleanups

2014-08-12 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com I had to look at the cursor code recently, and as usual I ended up doing bit of fixing and some cleanups. There's still more that needs doing, but I'll leave that for later and not continue down this path for now. While trying to figure out what

[Intel-gfx] [PATCH 4/4] drm/i915: Add support for variable cursor size on 845/865

2014-08-12 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com 845/865 support different cursor sizes as well, albeit a bit differently than later platforms. Add the necessary code to make them work. Untested due to lack of hardware. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 3/4] drm/i915: Unify ivb_update_cursor() and i9xx_update_cursor()

2014-08-12 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Ever since commit 5efb3e2838536832c9b6872512e6b6daf592cee9 Author: Ville Syrjälä ville.syrj...@linux.intel.com Date: Wed Apr 9 13:28:53 2014 +0300 drm/i915/chv: Add cursor pipe offsets the only difference between i9xx_update_cursor()

[Intel-gfx] [PATCH v4 4/4] drm/i915: Add support for variable cursor size on 845/865

2014-08-13 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com 845/865 support different cursor sizes as well, albeit a bit differently than later platforms. Add the necessary code to make them work. Untested due to lack of hardware. v2: Warn but accept invalid stride (Chris) Rewrite the cursor size

[Intel-gfx] [PATCH] drm/i915: Move vblank enable earlier and disable later

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com We changed to an interrupt based vblank wait (as opposed to polling) in: commit 44bd93a3d367913d883be6abba9a6e51a53c4e90 Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Fri Jul 25 23:36:44 2014 +0200 drm/i915: Use generic vblank wait

[Intel-gfx] [PATCH 00/16] drm/i915: 830M/ns201 fixes again

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Thomas asked me to repost my 830/ns2501 patches. So here they are. I added a few more patches (trickle feed and unused ring init) to fix some post-resume issues. The primary plane rmw elimination patches and some locking/load detect fixes already

[Intel-gfx] [PATCH 03/16] drm/i915: Idle unused rings on gen2/3 during init/resume

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com gen2/3 platforms have a boatload of rings we're not using. On my 830 the BIOS/hw can leave some of those active after resume which will prevent c3 entry. The ring is apparently considered active whenever head != tail even if the ring is disabled.

[Intel-gfx] [PATCH 01/16] drm/i915: Fix gen2 planes B and C max watermark value

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The max watermark value for gen2 planes B and C is 0x1f, instead of the 0x3f that plane A uses. Also check against the max even if the pipe is disabled since the FIFO size exceeds the plane B and C max watermark value. Signed-off-by: Ville

[Intel-gfx] [PATCH 02/16] drm/i915: Disable trickle feed for gen2/3

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com My 830 is unhappy with trickle feed enabled. The symptom is that the image on the screen shifts a bit to right occasionally. The BIOS initially disables trickle feed, but it gets reset during suspend, so we need to re-disable it ourselves. Juse

[Intel-gfx] [PATCH 06/16] drm/i915: ns2501 is on DVOB

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead of DVOC. FIXME: Maybe need to dig out the correct DVO port from VBT Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 2 +-

[Intel-gfx] [PATCH 04/16] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Just pass the intel_crtc around instead of dev_priv+pipe. Also make intel_wait_for_pipe_off() static since it's only used in intel_display.c. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c |

[Intel-gfx] [PATCH 08/16] drm/i915: Don't call DVO mode_set hook on DPMS changes

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Calling the mode_set hook on DPMS changes doesn't seem to be necessary for ns2501. Just drop it. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 4 1 file changed, 4 deletions(-) diff --git

[Intel-gfx] [PATCH 07/16] drm/i915: Enable DVO between mode_set and dpms hooks

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com To more closely match the IEGD ns2501 driver behaviour, call the mode_set hook while the DVO port is still disabled, then enable the DVO port, and finally call the dpms hook. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH v3 05/16] drm/i915: Disable double wide even when leaving the pipe on

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Disable double wide even if the pipe quirk compels us to leave the pipe running. Double wide has certain implications for the plane assignments so best keep it off. Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010 when double

[Intel-gfx] [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/dvo_ns2501.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c index

[Intel-gfx] [PATCH 11/16] drm/i915: Init important ns2501 registers

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don't have a good one time init place in

[Intel-gfx] [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Try to use the same programming sequence as used by the IEGD driver. Also shovel the magic register values into a big static const array. The register values are actually the based on what the BIOS programs on the Fujitsu-Siemens Lifebook S6010.

[Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The spec says: For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in both the DPLL A Control Register

[Intel-gfx] [PATCH v2 15/16] drm/i915: Add pipe B force quirk for 830M

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com 830M has problems when some of the pipes are disabled. Namely if a plane, DVO port etc. is currently assigned to a disabled pipe, it can't moved to the other pipe until the current pipe is also enabled. To keep things simple just leave both pipes

[Intel-gfx] [PATCH 14/16] Revert drm/i915: Nuke pipe A quirk on i830M

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com 830 really does want the pipe A quirk. The planes and ports don't react to any register writes unless the pipe currently attached to them is running, so it's impossible to move them to the other pipe unless both pipes are running. Also it's

[Intel-gfx] [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes, 60Hz and 56Hz. The magic register values we have correspond to the 60Hz mode, and as I don't know how one would trick the VGA BIOS to set up the 56Hz mode we can't get the

[Intel-gfx] [PATCH 16/16] drm/i915: Preserve VGACNTR bits from the BIOS

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from S3 unless VGACNTR has been restore to the original value. The BIOS value in this case was 0x0124008E. Setting the VGA disable bit doesn't interfere with the S3 resume fortunately.

[Intel-gfx] [PATCH v2 2/4] drm/i915: Populate mem_freq in init_gt_powerwave()

2014-08-18 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com init_clock_gating() is too late to read out the mem_freq. We already want to print out the GPU MHz numbers before it's called. Move the mem_freq setup to init_gt_powersave(). v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines Signed-off-by:

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