Re: [Intel-gfx] [PATCH v4] drm/i915/ppgtt: Load address space after mi_set_context

2014-09-23 Thread Zhi Wang
Hi Michel: I'm doing a task which require LRIs to load root pointer around RCS context switch.My BDW CPU is C stepping. And what I found is MI_SET_CONTEXT instruction will save/restore PDP0/1/2/3. It's weired that as part of EXECLIST context, the EXECLIST PPGTT base context also appear in

[Intel-gfx] [PATCH] drm/i915: Add missed MI_BATCH_BUFFER_END in null state batch buffer.

2014-10-28 Thread Zhi Wang
) environment. Signed-off-by: Zhi Wang zhi.a.w...@intel.com --- drivers/gpu/drm/i915/i915_gem_render_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 98dcd94..3495b4b 100644

Re: [Intel-gfx] [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.

2015-02-11 Thread Zhi Wang
Thanks Daniel! :) 于 2015年02月11日 16:03, Daniel Vetter 写道: On Tue, Feb 10, 2015 at 05:11:36PM +0800, Zhi Wang wrote: This patch introduces 2 bit definitions of context save/restore control register. Thanks comments from David/Thomas/Daniel. Instead of Thanks just add the usual Suggested

[Intel-gfx] [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.

2015-02-10 Thread Zhi Wang
This patch introduces 2 bit definitions of context save/restore control register. Thanks comments from David/Thomas/Daniel. Signed-off-by: Zhi Wang zhi.a.w...@intel.com --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- drivers/gpu/drm/i915/intel_lrc.h | 2 ++ 2 files changed, 4 insertions(+), 1

Re: [Intel-gfx] looks like a issue in do_switch() and mi_set_context() in i915_gem_context.c?

2015-04-01 Thread Zhi Wang
Hi Chris: Thanks for the reply. :) I can understand that the backing storage is pinned at this time, as the reference counter of context object should not be zero. But for VMA, is there any chance that the vma will be unbinded from GGTT at this time by shrinker? I saw that

Re: [Intel-gfx] [PATCH] drm/i915: Also perform gpu reset under execlist mode.

2015-06-25 Thread Zhi Wang
Hi Chris: Thanks for the reply! I just dig the code. It looks there is no special code path for execlist shutdown. It has init_rings(), but doesn't have cleanup_rings(), only clean_ring(), which are called for each ring one by one when i915_gem_cleanup_ringbuffer() gets called. Do you

Re: [Intel-gfx] [PATCH] drm/i915: Also perform gpu reset under execlist mode.

2015-06-25 Thread Zhi Wang
Thanks! :D Thanks, Zhi. 于 06/25/15 21:42, Chris Wilson 写道: On Thu, Jun 25, 2015 at 05:56:58AM +0800, Zhi Wang wrote: Hi Chris: Thanks for the reply! I just dig the code. It looks there is no special code path for execlist shutdown. It has init_rings(), but doesn't have cleanup_rings

[Intel-gfx] Do we also need to reset HW when execlist mode is enabled?

2015-06-24 Thread Zhi Wang
Hi Experts: Recently we found that when i915 module got unloaded, when we were debugging some bugs in XenGT. It would not reset HW under execlist mode. I'm not sure if this is an issue. But if we keep loading/unloading module with the different submission mode, e.g. from execlist mode to

Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode.

2015-07-07 Thread Zhi Wang
Hi Chris and Mika: Thanks for the comments. I think that reset HW on module unload is an good idea. For now I think we should choose a proper position in the module unload sequence to reset HW. As GPU reset is render engine reset plus ring imrs(They will become to alll F after full GPU

[Intel-gfx] About the wait_for() macro in intel_drv.h

2015-07-15 Thread Zhi Wang
Hi Gurus: Recently we found that the wait_for() marco in intel_drv.h looks will cause dead lock. wait_for() macro will try to wait jiffies change in a condition check loop, but when local cpu interrupt is disabled, it seems the jiffies will never change under a uni-processor environment. And

Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode.

2015-07-07 Thread Zhi Wang
at 04:23:13AM +0800, Zhi Wang wrote: Hi Chris: How about this one? :) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c5349fa..013039e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1134,6 +1134,21 @@ int i915_driver_unload

Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode.

2015-07-07 Thread Zhi Wang
if the context saved by MI_SET_CONTEXT is just the power context in B-spec?If yes, why doest it looks like that? Thanks, Zhi. 于 07/07/15 20:10, Chris Wilson 写道: On Tue, Jul 07, 2015 at 04:32:53AM +0800, Zhi Wang wrote: Thanks for the comments!:) I'm wondering that why the GEN=5 is needed here

Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode.

2015-07-07 Thread Zhi Wang
); + intel_uncore_fini(dev); if (dev_priv-regs != NULL) pci_iounmap(dev-pdev, dev_priv-regs); 于 07/07/15 16:58, Chris Wilson 写道: On Tue, Jul 07, 2015 at 12:04:10AM +0800, Zhi Wang wrote: Hi Chris and Mika: Thanks for the comments. I think that reset HW on module

Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode.

2015-07-07 Thread Zhi Wang
, Chris Wilson 写道: On Tue, Jul 07, 2015 at 03:38:37AM +0800, Zhi Wang wrote: Hi Chris: Thanks for the comments! I can understand that we're concerned about regressions, so this is why I think put this reset in module unload path looks much safer. For safety, maybe we should only reset GPU

[Intel-gfx] Write GFX_FLSH_CNT after updating GGTT entries

2015-11-19 Thread Zhi Wang
Hi Gurus: I'm curious about the register GFX_FLSH_CNT(0x101008) in i915_gem_gtt.c. Does these register exist in recently generations? After digging into b-spec, it looks only BXT and CHV has this register. Does the desktop platform also have this register which needs to be written after

Re: [Intel-gfx] Water mark update need to wait for next VSYNC?

2015-09-06 Thread Zhi Wang
Hi William: There is a kind of display register marked as double-buffered. It means that HW will *not* latch the value in the register all the time. HW will only latch the value on the start of the vertical blank, or the time when pipe/plane are enabling. So you will see some code pieces

Re: [Intel-gfx] Water mark update need to wait for next VSYNC?

2015-09-06 Thread Zhi Wang
Thanks Ville! Learned from you guys. :) 于 09/06/15 19:50, Ville Syrjälä 写道: On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote: Hi William: There is a kind of display register marked as double-buffered. It means that HW will *not* latch the value in the register all the time. HW

Re: [Intel-gfx] Write GFX_FLSH_CNT after updating GGTT entries

2015-11-19 Thread Zhi Wang
/15 18:35, Ville Syrjälä wrote: On Thu, Nov 19, 2015 at 06:20:23PM +0800, Zhi Wang wrote: Hi Gurus: I'm curious about the register GFX_FLSH_CNT(0x101008) in i915_gem_gtt.c. Does these register exist in recently generations? After digging into b-spec, it looks only BXT and CHV has this register

Re: [Intel-gfx] Write GFX_FLSH_CNT after updating GGTT entries

2015-11-19 Thread Zhi Wang
, IRQ 27 Memory at f740 (64-bit, non-prefetchable) [size=4M] So this should be our own magic to play WC on a non-prefechable BAR especially for GGTT MMIOs? Thanks, Zhi. On 11/19/15 21:26, Ville Syrjälä wrote: On Thu, Nov 19, 2015 at 09:04:11PM +0800, Zhi Wang wrote: Hi Ville: Thanks

[Intel-gfx] [PATCH v8 06/10] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-08 Thread Zhi Wang
; Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/dr

[Intel-gfx] [PATCH v8 04/10] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-08 Thread Zhi Wang
.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/drm/i915/Makefile| 5 ++ drivers/gpu/drm/i915/gvt/Make

[Intel-gfx] [PATCH v8 07/10] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-08 Thread Zhi Wang
gt; Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 12 drivers/gp

[Intel-gfx] [PATCH v8 08/10] drm/i915: Introduce execlist context status change notification

2016-06-08 Thread Zhi Wang
e notifier header, so it could be switched on/off at runtime. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.urs

[Intel-gfx] [PATCH v8 09/10] drm/i915: Support LRC context single submission

2016-06-08 Thread Zhi Wang
hti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 15 +++ 2 files changed, 16 i

[Intel-gfx] [PATCH v8 03/10] drm/i915: Fold vGPU active check into inner functions

2016-06-08 Thread Zhi Wang
ian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 --- drivers/gpu/drm/i915/i915_vgpu.c| 13 + drivers/gpu/drm/i915/i915_vgpu.h| 4 ++-- 3 files changed, 15 insertions(+), 13 deletions(-) diff --gi

[Intel-gfx] [PATCH v8 00/10] Introduce the implementation of GVT context

2016-06-08 Thread Zhi Wang
-gfx/2015-September/075397.html Bing Niu (1): drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang (9): drm/i915: Factor out i915_pvinfo.h drm/i915: Use offsetof() to calculate the offset of members in PVINFO page drm/i915: Fold vGPU active check into inner functions

[Intel-gfx] [PATCH v8 02/10] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-08 Thread Zhi Wang
Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 68bdf60..7b3c

[Intel-gfx] [PATCH v8 05/10] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-08 Thread Zhi Wang
ilson.co.uk> Cc: Kevin Tian <kevin.t...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Signed-off-by: Bing Niu <bing....@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c | 23 +---

[Intel-gfx] [PATCH v8 10/10] drm/i915: Introduce GVT context creation API

2016-06-08 Thread Zhi Wang
gic of GEM context creation service and LRC context creation service to create the GVT context. Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zh

[Intel-gfx] [PATCH v8 01/10] drm/i915: Factor out i915_pvinfo.h

2016-06-08 Thread Zhi Wang
structure (Joonas) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/drm/i915/i915_vgpu.h | 86 +---

[Intel-gfx] [PATCH v9 06/10] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-09 Thread Zhi Wang
htinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 2 +- 3 fil

[Intel-gfx] [PATCH v9 10/10] drm/i915: Introduce GVT context creation API

2016-06-09 Thread Zhi Wang
;tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 34 + 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH v9 05/10] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-09 Thread Zhi Wang
linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Kevin Tian <kevin.t...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Signed-off-by: Bing Niu <bing@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c |

[Intel-gfx] [PATCH v9 04/10] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-09 Thread Zhi Wang
.@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/dr

[Intel-gfx] [PATCH v9 03/10] drm/i915: Fold vGPU active check into inner functions

2016-06-09 Thread Zhi Wang
ian <kevin.t...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---

[Intel-gfx] [PATCH v9 09/10] drm/i915: Support LRC context single submission

2016-06-09 Thread Zhi Wang
hti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers

[Intel-gfx] [PATCH v9 08/10] drm/i915: Introduce execlist context status change notification

2016-06-09 Thread Zhi Wang
;ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 22

[Intel-gfx] [PATCH v9 07/10] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-09 Thread Zhi Wang
intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + driv

[Intel-gfx] [PATCH v9 01/10] drm/i915: Factor out i915_pvinfo.h

2016-06-09 Thread Zhi Wang
structure (Joonas) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/

[Intel-gfx] [PATCH v9 02/10] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-09 Thread Zhi Wang
Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH v9 00/10] Introduce the implementation of GVT context

2016-06-09 Thread Zhi Wang
! Reference - [1] https://01.org/igvt-g [2] http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html [3] http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html Bing Niu (1): drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang (9

[Intel-gfx] [PATCH v7 05/11] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-07 Thread Zhi Wang
ove empty and unused functions. - Replace magic number with marcos. - Set GVT-g in kernel config to "n" by default. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/Kconfig | 22 + drivers/gpu/drm/i915/Makefile| 5 ++ drivers/gpu/drm/i9

[Intel-gfx] [PATCH v7 04/11] drm/i915: Add teardown path in intel_vgt_ballon()

2016-06-07 Thread Zhi Wang
This function needs to be changed to have a proper goto teardown path. Destructors/fini functions are only expected to be called after a successful initialization, so calling it at random phase in init function is bad. (Joonas) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/g

[Intel-gfx] [PATCH v7 08/11] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-07 Thread Zhi Wang
ssing mode bits into intel_lrc.h. (Chris) v5: - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 2 ++ drivers/gpu/drm/i915/i915_re

[Intel-gfx] [PATCH v7 11/11] drm/i915: Introduce GVT context creation API

2016-06-07 Thread Zhi Wang
ment about the ring buffer size. (Joonas) v2: Mostly based on Daniel's idea. Call the refactored core logic of GEM context creation service and LRC context creation service to create the GVT context. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH v7 03/11] drm/i915: Fold vGPU active check into inner functions

2016-06-07 Thread Zhi Wang
v5: - Let functions take struct drm_i915_private *. (Tvrtko) - Fold vGPU related active check into the inner functions. (Kevin) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 --- drivers/gpu/drm/i915/i915_vgpu.c

[Intel-gfx] [PATCH v7 06/11] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-07 Thread Zhi Wang
meters. (Joonas) v2: - Address all coding-style comments from Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu <bing@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --

[Intel-gfx] [PATCH v7 07/11] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-07 Thread Zhi Wang
This patch introduces an option for configuring the ring buffer size of a LRC context after the context creation. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH v7 10/11] drm/i915: Support LRC context single submission

2016-06-07 Thread Zhi Wang
: - Fix typos in commit message. (Joonas) v6: - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/dr

[Intel-gfx] [PATCH v7 09/11] drm/i915: Introduce execlist context status change notification

2016-06-07 Thread Zhi Wang
. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 25 +++

[Intel-gfx] [PATCH v7 01/11] drm/i915: Factor out i915_pvinfo.h

2016-06-07 Thread Zhi Wang
structure (Joonas) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/drm/i915/i915_vgpu.h | 86 +--- 2 files changed, 114 insertions(+), 85 deletions(-) create mode 100644

[Intel-gfx] [PATCH v7 00/11] Introduce the implementation of GVT context

2016-06-07 Thread Zhi Wang
(1): drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang (10): drm/i915: Factor out i915_pvinfo.h drm/i915: Use offsetof() to calculate the offset of members in PVINFO page drm/i915: Fold vGPU active check into inner functions drm/i915: Add teardown path

[Intel-gfx] [PATCH v7 02/11] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-07 Thread Zhi Wang
To get the offset of the members in PVINFO page, offsetof() looks much better than the tricky approach in current code. v7: - Move "offsetof()" modification into a dedicated patch. (Joonas) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.

[Intel-gfx] [PATCH v10 04/10] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-09 Thread Zhi Wang
.@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/dr

[Intel-gfx] [PATCH v10 05/10] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-09 Thread Zhi Wang
linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Kevin Tian <kevin.t...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Signed-off-by: Bing Niu <bing@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c |

[Intel-gfx] [PATCH v10 07/10] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-09 Thread Zhi Wang
by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> (v9) Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm

[Intel-gfx] [PATCH v10 02/10] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-09 Thread Zhi Wang
Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH v10 10/10] drm/i915: Introduce GVT context creation API

2016-06-09 Thread Zhi Wang
;tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 34 + 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH v10 01/10] drm/i915: Factor out i915_pvinfo.h

2016-06-09 Thread Zhi Wang
structure (Joonas) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/

[Intel-gfx] [PATCH v10 08/10] drm/i915: Introduce execlist context status change notification

2016-06-09 Thread Zhi Wang
.@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/

[Intel-gfx] [PATCH v10 03/10] drm/i915: Fold vGPU active check into inner functions

2016-06-09 Thread Zhi Wang
ian <kevin.t...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---

[Intel-gfx] [PATCH v10 06/10] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-09 Thread Zhi Wang
htinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 2 +- 3 fil

[Intel-gfx] [PATCH v10 09/10] drm/i915: Support LRC context single submission

2016-06-09 Thread Zhi Wang
hti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers

[Intel-gfx] [PATCH v10 00/10] Introduce the implementation of GVT context

2016-06-09 Thread Zhi Wang
partition for GVT-g Zhi Wang (9): drm/i915: Factor out i915_pvinfo.h drm/i915: Use offsetof() to calculate the offset of members in PVINFO page drm/i915: Fold vGPU active check into inner functions drm/i915: gvt: Introduce the basic architecture of GVT-g drm/i915: Make ring buffer size

[Intel-gfx] [PATCH v11 5/9] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-14 Thread Zhi Wang
htinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 2 +- 3 fil

[Intel-gfx] [PATCH v11 2/9] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-14 Thread Zhi Wang
Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH v11 4/9] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-14 Thread Zhi Wang
.@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/dr

[Intel-gfx] [PATCH v11 7/9] drm/i915: Introduce execlist context status change notification

2016-06-14 Thread Zhi Wang
.@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/

[Intel-gfx] [PATCH v11 3/9] drm/i915: Fold vGPU active check into inner functions

2016-06-14 Thread Zhi Wang
ian <kevin.t...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---

[Intel-gfx] [PATCH v11 6/9] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-14 Thread Zhi Wang
by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> (v9) Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm

[Intel-gfx] [PATCH v11 9/9] drm/i915: Introduce GVT context creation API

2016-06-14 Thread Zhi Wang
;tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 34 + 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH v11 8/9] drm/i915: Support LRC context single submission

2016-06-14 Thread Zhi Wang
hti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers

[Intel-gfx] [PATCH v11 0/9] Introduce the implementation of GVT context

2016-06-14 Thread Zhi Wang
ake iGVT-g a great component in i915 to support graphics virtualization. Thanks! Reference - [1] https://01.org/igvt-g [2] http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html [3] http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html Zhi Wang

[Intel-gfx] [PATCH v11 1/9] drm/i915: Factor out i915_pvinfo.h

2016-06-14 Thread Zhi Wang
structure (Joonas) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/

[Intel-gfx] [PATCH 8/9] drm/i915: Support LRC context single submission

2016-06-02 Thread Zhi Wang
: - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 15 +++ 2 files c

[Intel-gfx] [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-02 Thread Zhi Wang
. - Replace customized info/warn/debug macros with DRM macros. - Document all non-static functions like i915. - Remove empty and unused functions. - Replace magic number with marcos. - Set GVT-g in kernel config to "n" by default. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- driv

[Intel-gfx] [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h

2016-06-02 Thread Zhi Wang
As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g host (GVT-g kernel device model), factor it out for better code structure. v3: Take Joonas's comments: - Use offsetof to calculate the member offset of PVINFO structure Signed-off-by: Zhi Wang <zhi.a.w...@intel.

[Intel-gfx] [PATCH 0/9] Introduce the implementation of GVT context

2016-06-02 Thread Zhi Wang
: Introduce host graphics memory partition for GVT-g Zhi Wang (8): drm/i915: Factor out i915_pvinfo.h drm/i915: Fold vGPU active check into inner functions drm/i915: gvt: Introduce the basic architecture of GVT-g drm/i915: Make ring buffer size of a LRC context configurable drm/i915: Make

[Intel-gfx] [PATCH 2/9] drm/i915: Fold vGPU active check into inner functions

2016-06-02 Thread Zhi Wang
v5: - Let functions take struct drm_i915_private *. (Tvrtko) - Fold vGPU related active check into the inner functions. (Kevin) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 --- drivers/gpu/drm/i915/i915_vgpu.c

[Intel-gfx] [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-02 Thread Zhi Wang
Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu <bing@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c | 23 +-

[Intel-gfx] [PATCH 5/9] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-02 Thread Zhi Wang
This patch introduces an option for configuring the ring buffer size of a LRC context after the context creation. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 6/9] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-02 Thread Zhi Wang
of a LRC context should be configurable under this case. v6: - Directly save the addressing mode bits inside i915_gem_context. (Chris) - Move the LRC context addressing mode bits into intel_lrc.h. (Chris) v5: - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko) Signed-off-by: Zhi Wang

[Intel-gfx] [PATCH 7/9] drm/i915: Introduce execlist context status change notification

2016-06-02 Thread Zhi Wang
notifier header, so it could be switched on/off at runtime. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 24 +++

[Intel-gfx] [PATCH 9/9] drm/i915: Introduce GVT context creation API

2016-06-02 Thread Zhi Wang
M_I915_GVT is enabled. (Tvrtko) - Rebase the code into new repo. - Add a comment about the ring buffer size. (Joonas) v2: Mostly based on Daniel's idea. Call the refactored core logic of GEM context creation service and LRC context creation service to create the GVT context. Signed-off-by: Zhi Wan

[Intel-gfx] [PATCH v6 4/9] drm/i915: Introduce host graphics memory partition for GVT-g

2016-06-02 Thread Zhi Wang
Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu <bing@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c | 23 +-

[Intel-gfx] [PATCH v6 5/9] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-02 Thread Zhi Wang
This patch introduces an option for configuring the ring buffer size of a LRC context after the context creation. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH v6 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g

2016-06-02 Thread Zhi Wang
. - Replace customized info/warn/debug macros with DRM macros. - Document all non-static functions like i915. - Remove empty and unused functions. - Replace magic number with marcos. - Set GVT-g in kernel config to "n" by default. Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- driv

[Intel-gfx] [PATCH v6 2/9] drm/i915: Fold vGPU active check into inner functions

2016-06-02 Thread Zhi Wang
v5: - Let functions take struct drm_i915_private *. (Tvrtko) - Fold vGPU related active check into the inner functions. (Kevin) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 --- drivers/gpu/drm/i915/i915_vgpu.c

[Intel-gfx] [PATCH v6 0/9] Introduce the implementation of GVT context

2016-06-02 Thread Zhi Wang
: Introduce host graphics memory partition for GVT-g Zhi Wang (8): drm/i915: Factor out i915_pvinfo.h drm/i915: Fold vGPU active check into inner functions drm/i915: gvt: Introduce the basic architecture of GVT-g drm/i915: Make ring buffer size of a LRC context configurable drm/i915: Make

[Intel-gfx] [PATCH v6 1/9] drm/i915: Factor out i915_pvinfo.h

2016-06-02 Thread Zhi Wang
As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g host (GVT-g kernel device model), factor it out for better code structure. v3: Take Joonas's comments: - Use offsetof to calculate the member offset of PVINFO structure Signed-off-by: Zhi Wang <zhi.a.w...@intel.

[Intel-gfx] [PATCH v6 8/9] drm/i915: Support LRC context single submission

2016-06-02 Thread Zhi Wang
: - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 15 +++ 2 files c

[Intel-gfx] [PATCH v6 7/9] drm/i915: Introduce execlist context status change notification

2016-06-02 Thread Zhi Wang
notifier header, so it could be switched on/off at runtime. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 24 +++

[Intel-gfx] [PATCH v6 9/9] drm/i915: Introduce GVT context creation API

2016-06-02 Thread Zhi Wang
M_I915_GVT is enabled. (Tvrtko) - Rebase the code into new repo. - Add a comment about the ring buffer size. (Joonas) v2: Mostly based on Daniel's idea. Call the refactored core logic of GEM context creation service and LRC context creation service to create the GVT context. Signed-off-by: Zhi Wan

[Intel-gfx] [PATCH v6 6/9] drm/i915: Make addressing mode bits in context descriptor configurable

2016-06-02 Thread Zhi Wang
of a LRC context should be configurable under this case. v6: - Directly save the addressing mode bits inside i915_gem_context. (Chris) - Move the LRC context addressing mode bits into intel_lrc.h. (Chris) v5: - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko) Signed-off-by: Zhi Wang

[Intel-gfx] [PATCH v12 0/9] Introduce the implementation of GVT context

2016-06-16 Thread Zhi Wang
075397.html Zhi Wang (9): drm/i915: Factor out i915_pvinfo.h drm/i915: Use offsetof() to calculate the offset of members in PVINFO page drm/i915: Fold vGPU active check into inner functions drm/i915: gvt: Introduce the basic architecture of GVT-g drm/i915: Make ring buffer size of a LRC c

[Intel-gfx] [PATCH v12 1/9] drm/i915: Factor out i915_pvinfo.h

2016-06-16 Thread Zhi Wang
structure (Joonas) Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 113 + drivers/gpu/

[Intel-gfx] [PATCH v12 3/9] drm/i915: Fold vGPU active check into inner functions

2016-06-16 Thread Zhi Wang
ian <kevin.t...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Kevin Tian <kevin.t...@intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---

[Intel-gfx] [PATCH v12 2/9] drm/i915: Use offsetof() to calculate the offset of members in PVINFO page

2016-06-16 Thread Zhi Wang
Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH v12 8/9] drm/i915: Support LRC context single submission

2016-06-16 Thread Zhi Wang
hti...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers

[Intel-gfx] [PATCH v12 5/9] drm/i915: Make ring buffer size of a LRC context configurable

2016-06-16 Thread Zhi Wang
htinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Zhi Wang <zhi.a.w...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/intel_lrc.c| 2 +- 3 fil

  1   2   3   4   5   >