[Intel-gfx] [PATCH] drm/i915/gt: Set the PD again for Haswell
And Haswell still occasionally forgets it is meant to be using a new
page directory, so repeat ourselves a little louder.
<7> [509.919864] heartbeat rcs0 heartbeat {prio:-2147483645} not ticking
<7> [509.919895] heartbeat Awake? 8
<7> [509.919903] heartbeat Barriers?: no
<7> [509.919912] heartbeat Heartbeat: 3008 ms ago
<7> [509.919930] heartbeat Reset count: 0 (global 0)
<7> [509.919937] heartbeat Requests:
<7> [509.921008] heartbeat active a7eb:56e1* @ 5847ms:
<7> [509.921157] heartbeat ring->start: 0x1000
<7> [509.921164] heartbeat ring->head: 0x1610
<7> [509.921170] heartbeat ring->tail: 0x23d8
<7> [509.921176] heartbeat ring->emit: 0x23d8
<7> [509.921182] heartbeat ring->space: 0x2570
<7> [509.921189] heartbeat ring->hwsp: 0x7fffe100
<7> [509.921197] heartbeat [head 1628, postfix 1738, tail 1750, batch
0x_]:
<7> [509.921289] heartbeat [] 7a02 0012 7a02
01154c1e 7080
<7> [509.921299] heartbeat [0020] 1101 2220 1241 2220
7000 1101
<7> [509.921308] heartbeat [0040] 2228 6e90 7a02 0012
7a02 01154c1e
<7> [509.921317] heartbeat [0060] 7080 1241 2228 7000
7a02 0012
<7> [509.921326] heartbeat [0080] 7a02 01154c1e 7080
7a02 001010a1
<7> [509.921335] heartbeat [00a0] 7080 0400 1105 00022050
00010001 00012050 00010001
<7> [509.921345] heartbeat [00c0] 0001a050 00010001 0c00 459a110c
1105 00022050
<7> [509.921354] heartbeat [00e0] 0001 00012050 0001 0001a050 0001
1241 0001a050 7000
<7> [509.921363] heartbeat [0100] 0401 18802100 7a02
011050a1 7fffe100 56e1
<7> [509.921370] heartbeat [0120] 0100
<7> [509.921538] heartbeat MMIO base: 0x2000
<7> [509.921682] heartbeat CCID: 0x3fa0110d
<7> [509.922342] heartbeat RING_START: 0x1000
<7> [509.922353] heartbeat RING_HEAD: 0x1628
<7> [509.922366] heartbeat RING_TAIL: 0x23d8
<7> [509.922381] heartbeat RING_CTL: 0x3001
<7> [509.922396] heartbeat RING_MODE: 0x4000
<7> [509.922408] heartbeat RING_IMR: ffde
<7> [509.922421] heartbeat ACTHD: 0x_30e01628
<7> [509.922434] heartbeat BBADDR: 0x_4004
<7> [509.922446] heartbeat DMA_FADDR: 0x_2800
<7> [509.922458] heartbeat IPEIR: 0x
<7> [509.922470] heartbeat IPEHR: 0x780c
<7> [509.922642] heartbeat PP_DIR_BASE: 0x6e70
<7> [509.922652] heartbeat PP_DIR_BASE_READ: 0x
<7> [509.922662] heartbeat PP_DIR_DCLV: 0x
<7> [509.922678] heartbeat E a7eb:56e1* @ 5849ms:
<7> [509.922689] heartbeat E a7eb:56e2- @ 5849ms:
<7> [509.922698] heartbeat E a7eb:56e3 @ 5848ms:
<7> [509.922707] heartbeat E a7eb:56e4 @ 5848ms:
<7> [509.922715] heartbeat E a7eb:56e5 @ 5847ms:
<7> [509.922724] heartbeat E a7eb:56e6 @ 5846ms:
<7> [509.922735] heartbeat E a7eb:56e7 @ 5846ms:
<7> [509.922744] heartbeat ...skipping 4 executing requests...
<7> [509.922754] heartbeat E a7eb:56ec @ 3010ms:
<7> [509.922796] heartbeat HWSP:
<7> [509.922807] heartbeat [] 0001
<7> [509.922817] heartbeat [0020]
<7> [509.922826] heartbeat *
<7> [509.922836] heartbeat [0100] 56e0
<7> [509.922845] heartbeat [0120]
<7> [509.922851] heartbeat *
<7> [509.922870] heartbeat Idle? no
<7> [509.922878] heartbeat Signals:
<7> [509.923000] heartbeat [a7eb:56e2] @ 5850ms
Here, we have a failed context restore after the PD switch, but note
that the PP_DIR_BASE register does not match the LRI in the ring.
Bump it to 8 loops, and with that Baytrail starts passing the sanity
checks.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 51 +--
drivers/gpu/drm/i915/i915_pci.c | 2 +-
2 files changed, 15 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index dcdeef0a776f..a5c1a1bd2f35 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1366,7 +1366,7 @@ static int load_pd_dir(struct i915_request *rq, const
struct i915_ppgtt *ppgtt)
const struct intel_engine_cs * const engine = rq->engine;
u32 *cs;
[Intel-gfx] [PATCH] drm/i915/gt: Set the PD again for Haswell
And Haswell still occasionally forgets it is meant to be using a new
page directory, so repeat ourselves a little louder.
<7> [509.919864] heartbeat rcs0 heartbeat {prio:-2147483645} not ticking
<7> [509.919895] heartbeat Awake? 8
<7> [509.919903] heartbeat Barriers?: no
<7> [509.919912] heartbeat Heartbeat: 3008 ms ago
<7> [509.919930] heartbeat Reset count: 0 (global 0)
<7> [509.919937] heartbeat Requests:
<7> [509.921008] heartbeat active a7eb:56e1* @ 5847ms:
<7> [509.921157] heartbeat ring->start: 0x1000
<7> [509.921164] heartbeat ring->head: 0x1610
<7> [509.921170] heartbeat ring->tail: 0x23d8
<7> [509.921176] heartbeat ring->emit: 0x23d8
<7> [509.921182] heartbeat ring->space: 0x2570
<7> [509.921189] heartbeat ring->hwsp: 0x7fffe100
<7> [509.921197] heartbeat [head 1628, postfix 1738, tail 1750, batch
0x_]:
<7> [509.921289] heartbeat [] 7a02 0012 7a02
01154c1e 7080
<7> [509.921299] heartbeat [0020] 1101 2220 1241 2220
7000 1101
<7> [509.921308] heartbeat [0040] 2228 6e90 7a02 0012
7a02 01154c1e
<7> [509.921317] heartbeat [0060] 7080 1241 2228 7000
7a02 0012
<7> [509.921326] heartbeat [0080] 7a02 01154c1e 7080
7a02 001010a1
<7> [509.921335] heartbeat [00a0] 7080 0400 1105 00022050
00010001 00012050 00010001
<7> [509.921345] heartbeat [00c0] 0001a050 00010001 0c00 459a110c
1105 00022050
<7> [509.921354] heartbeat [00e0] 0001 00012050 0001 0001a050 0001
1241 0001a050 7000
<7> [509.921363] heartbeat [0100] 0401 18802100 7a02
011050a1 7fffe100 56e1
<7> [509.921370] heartbeat [0120] 0100
<7> [509.921538] heartbeat MMIO base: 0x2000
<7> [509.921682] heartbeat CCID: 0x3fa0110d
<7> [509.922342] heartbeat RING_START: 0x1000
<7> [509.922353] heartbeat RING_HEAD: 0x1628
<7> [509.922366] heartbeat RING_TAIL: 0x23d8
<7> [509.922381] heartbeat RING_CTL: 0x3001
<7> [509.922396] heartbeat RING_MODE: 0x4000
<7> [509.922408] heartbeat RING_IMR: ffde
<7> [509.922421] heartbeat ACTHD: 0x_30e01628
<7> [509.922434] heartbeat BBADDR: 0x_4004
<7> [509.922446] heartbeat DMA_FADDR: 0x_2800
<7> [509.922458] heartbeat IPEIR: 0x
<7> [509.922470] heartbeat IPEHR: 0x780c
<7> [509.922642] heartbeat PP_DIR_BASE: 0x6e70
<7> [509.922652] heartbeat PP_DIR_BASE_READ: 0x
<7> [509.922662] heartbeat PP_DIR_DCLV: 0x
<7> [509.922678] heartbeat E a7eb:56e1* @ 5849ms:
<7> [509.922689] heartbeat E a7eb:56e2- @ 5849ms:
<7> [509.922698] heartbeat E a7eb:56e3 @ 5848ms:
<7> [509.922707] heartbeat E a7eb:56e4 @ 5848ms:
<7> [509.922715] heartbeat E a7eb:56e5 @ 5847ms:
<7> [509.922724] heartbeat E a7eb:56e6 @ 5846ms:
<7> [509.922735] heartbeat E a7eb:56e7 @ 5846ms:
<7> [509.922744] heartbeat ...skipping 4 executing requests...
<7> [509.922754] heartbeat E a7eb:56ec @ 3010ms:
<7> [509.922796] heartbeat HWSP:
<7> [509.922807] heartbeat [] 0001
<7> [509.922817] heartbeat [0020]
<7> [509.922826] heartbeat *
<7> [509.922836] heartbeat [0100] 56e0
<7> [509.922845] heartbeat [0120]
<7> [509.922851] heartbeat *
<7> [509.922870] heartbeat Idle? no
<7> [509.922878] heartbeat Signals:
<7> [509.923000] heartbeat [a7eb:56e2] @ 5850ms
Here, we have a failed context restore after the PD switch, but note
that the PP_DIR_BASE register does not match the LRI in the ring.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 51 +--
1 file changed, 14 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index dcdeef0a776f..8bfee09dd0e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1366,7 +1366,7 @@ static int load_pd_dir(struct i915_request *rq, const
struct i915_ppgtt *ppgtt)
const struct intel_engine_cs * const engine = rq->engine;
u32 *cs;
- cs = intel_ring_begin(rq, 10);
+ cs = intel_ring_begin(rq, 12);
if (IS_ERR(cs))
return PTR_ER
[Intel-gfx] [PATCH] drm/i915/gt: Set the PD again for Haswell
And Haswell still occasionally forgets it is meant to be using a new
page directory, so repeat ourselves a little louder.
<7> [509.919864] heartbeat rcs0 heartbeat {prio:-2147483645} not ticking
<7> [509.919895] heartbeat Awake? 8
<7> [509.919903] heartbeat Barriers?: no
<7> [509.919912] heartbeat Heartbeat: 3008 ms ago
<7> [509.919930] heartbeat Reset count: 0 (global 0)
<7> [509.919937] heartbeat Requests:
<7> [509.921008] heartbeat active a7eb:56e1* @ 5847ms:
<7> [509.921157] heartbeat ring->start: 0x1000
<7> [509.921164] heartbeat ring->head: 0x1610
<7> [509.921170] heartbeat ring->tail: 0x23d8
<7> [509.921176] heartbeat ring->emit: 0x23d8
<7> [509.921182] heartbeat ring->space: 0x2570
<7> [509.921189] heartbeat ring->hwsp: 0x7fffe100
<7> [509.921197] heartbeat [head 1628, postfix 1738, tail 1750, batch
0x_]:
<7> [509.921289] heartbeat [] 7a02 0012 7a02
01154c1e 7080
<7> [509.921299] heartbeat [0020] 1101 2220 1241 2220
7000 1101
<7> [509.921308] heartbeat [0040] 2228 6e90 7a02 0012
7a02 01154c1e
<7> [509.921317] heartbeat [0060] 7080 1241 2228 7000
7a02 0012
<7> [509.921326] heartbeat [0080] 7a02 01154c1e 7080
7a02 001010a1
<7> [509.921335] heartbeat [00a0] 7080 0400 1105 00022050
00010001 00012050 00010001
<7> [509.921345] heartbeat [00c0] 0001a050 00010001 0c00 459a110c
1105 00022050
<7> [509.921354] heartbeat [00e0] 0001 00012050 0001 0001a050 0001
1241 0001a050 7000
<7> [509.921363] heartbeat [0100] 0401 18802100 7a02
011050a1 7fffe100 56e1
<7> [509.921370] heartbeat [0120] 0100
<7> [509.921538] heartbeat MMIO base: 0x2000
<7> [509.921682] heartbeat CCID: 0x3fa0110d
<7> [509.922342] heartbeat RING_START: 0x1000
<7> [509.922353] heartbeat RING_HEAD: 0x1628
<7> [509.922366] heartbeat RING_TAIL: 0x23d8
<7> [509.922381] heartbeat RING_CTL: 0x3001
<7> [509.922396] heartbeat RING_MODE: 0x4000
<7> [509.922408] heartbeat RING_IMR: ffde
<7> [509.922421] heartbeat ACTHD: 0x_30e01628
<7> [509.922434] heartbeat BBADDR: 0x_4004
<7> [509.922446] heartbeat DMA_FADDR: 0x_2800
<7> [509.922458] heartbeat IPEIR: 0x
<7> [509.922470] heartbeat IPEHR: 0x780c
<7> [509.922642] heartbeat PP_DIR_BASE: 0x6e70
<7> [509.922652] heartbeat PP_DIR_BASE_READ: 0x
<7> [509.922662] heartbeat PP_DIR_DCLV: 0x
<7> [509.922678] heartbeat E a7eb:56e1* @ 5849ms:
<7> [509.922689] heartbeat E a7eb:56e2- @ 5849ms:
<7> [509.922698] heartbeat E a7eb:56e3 @ 5848ms:
<7> [509.922707] heartbeat E a7eb:56e4 @ 5848ms:
<7> [509.922715] heartbeat E a7eb:56e5 @ 5847ms:
<7> [509.922724] heartbeat E a7eb:56e6 @ 5846ms:
<7> [509.922735] heartbeat E a7eb:56e7 @ 5846ms:
<7> [509.922744] heartbeat ...skipping 4 executing requests...
<7> [509.922754] heartbeat E a7eb:56ec @ 3010ms:
<7> [509.922796] heartbeat HWSP:
<7> [509.922807] heartbeat [] 0001
<7> [509.922817] heartbeat [0020]
<7> [509.922826] heartbeat *
<7> [509.922836] heartbeat [0100] 56e0
<7> [509.922845] heartbeat [0120]
<7> [509.922851] heartbeat *
<7> [509.922870] heartbeat Idle? no
<7> [509.922878] heartbeat Signals:
<7> [509.923000] heartbeat [a7eb:56e2] @ 5850ms
Here, we have a failed context restore after the PD switch, but note
that the PP_DIR_BASE register does not match the LRI in the ring.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 38 +--
1 file changed, 9 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index dcdeef0a776f..451b304f2436 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1366,7 +1366,7 @@ static int load_pd_dir(struct i915_request *rq, const
struct i915_ppgtt *ppgtt)
const struct intel_engine_cs * const engine = rq->engine;
u32 *cs;
- cs = intel_ring_begin(rq, 10);
+ cs = intel_ring_begin(rq, 12);
if (IS_ERR(cs))
return PTR_ERR
