Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-05-11 Thread Mika Kuoppala 
Oscar Mateo  writes:

> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
>   - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>   - Squashed with this patch:
>   drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni 
>   - Squashed with this patch:
>   drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo 
>   - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
>   - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
>   - Wrap the commit message
>   - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
> v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
> v9:
>   - C, not lisp (Chris)
>   - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
>
> Signed-off-by: Oscar Mateo 
> Cc: Rodrigo Vivi 
> Cc: Tomasz Lis 
> Cc: Mika Kuoppala 
> Cc: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  9 +++
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  6 ++---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
>  drivers/gpu/drm/i915/intel_workarounds.c | 46 
> 
>  7 files changed, 69 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 04e2780..ad79d5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_CNL_REVID(p, since, until) \
>   (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>  
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1
> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
>  /*
>   * The genX designation typically refers to the render engine, so render
>   * capability related checks should use IS_GEN, while display and other 
> checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c879bfd..ea30e84 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct 
> drm_i915_private *dev_priv)
>* called on driver load and after a GPU reset, so you can place
>* workarounds here even if they get overwritten by GPU reset.
>*/
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>   if (IS_BROADWELL(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>   else if (IS_CHERRYVIEW(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> - I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>   else if (IS_GEN9_LP(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> + else if (INTEL_GEN(dev_priv) >= 9)
> + I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>  
>   /*
>* To support 64K PTEs we need to first enable the use of the
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 085928c..2b22d4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7238,6 +7238,7 @@ enum {
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0 _MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_MODE _MMIO(0xE5F4)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE  (1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE  (1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 911f288..920752a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct 
> intel_engine_cs *engine)
>   return -EINVAL;
>  
>   switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
>   case 10:
>   wa_bb_fn[0] = gen10_init_indirectctx_bb;
>   wa_bb_fn[1] = NULL;
> diff --git a/

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-05-08 Thread Oscar Mateo 
Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
  - C, not lisp (Chris)
  - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)

Signed-off-by: Oscar Mateo 
Cc: Rodrigo Vivi 
Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  6 ++---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 
 7 files changed, 69 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e2780..ad79d5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2469,6 +2469,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c879bfd..ea30e84 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2137,15 +2137,15 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
-   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+   else if (INTEL_GEN(dev_priv) >= 9)
+   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 
/*
 * To support 64K PTEs we need to first enable the use of the
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 085928c..2b22d4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_MODE   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 911f288..920752a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1665,6 +1665,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-05-04 Thread Tvrtko Ursulin 


On 02/05/2018 21:34, Oscar Mateo wrote:

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
   - Since it has been fixed already in upstream, removed the TODO
 comment about WA_SET_BIT for WaInPlaceDecompressionHang.
   - Squashed with this patch:
   drm/i915/icl: add icelake_init_clock_gating()
 from Paulo Zanoni 
   - Squashed with this patch:
   drm/i915/icl: WaForceEnableNonCoherent
 from Oscar Mateo 
   - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
 applies to B0 as well.
   - WaPipeControlBefore3DStateSamplePattern WABB was being applied
 to ICL incorrectly.
v4:
   - Wrap the commit message
   - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)

Cc: Rodrigo Vivi 
Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/i915_drv.h  |  9 +++
  drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
  drivers/gpu/drm/i915/i915_reg.h  |  1 +
  drivers/gpu/drm/i915/intel_lrc.c |  2 ++
  drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
  drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
  drivers/gpu/drm/i915/intel_workarounds.c | 46 
  7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 193176b..7a3b0b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
  #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
  
+#define ICL_REVID_A0		0x0

+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
  /*
   * The genX designation typically refers to the render engine, so render
   * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);


Sounds like:

if (IS_BROADWELL)
else if (IS_CHERRYVIEW)
else if (IS_GEN9_LP)
else if (IS_GEN >= 9) /* Here's the improvement */

Just a drive by, sorry. :)

Regards,

Tvrtko


diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..454009f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
  /* GEN8 chicken */
  #define HDC_CHICKEN0  _MMIO(0x7300)
  #define CNL_HDC_CHICKEN0  _MMIO(0xE5F0)
+#define ICL_HDC_MODE   _MMIO(0xE5F4)
  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE   (1<<15)
  #define  HDC_FENCE_DEST_SLM_DISABLE   (1<<14)
  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED  (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 513aee6..d5fab47 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
  
  	switch (INTEL_GEN(engine->i915)) {

+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-05-02 Thread Oscar Mateo 
Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)

Cc: Rodrigo Vivi 
Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 
 7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 193176b..7a3b0b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..454009f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_MODE   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 513aee6..d5fab47 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_CANNONLAKE(dev_priv))
+   if (IS_ICELAKE(dev_priv))
+   dev_priv->dis

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-30 Thread Oscar Mateo 

On 04/26/2018 08:01 AM, Mika Kuoppala wrote:

Oscar Mateo  writes:


Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
   - Since it has been fixed already in upstream, removed the TODO
 comment about WA_SET_BIT for WaInPlaceDecompressionHang.
   - Squashed with this patch:
   drm/i915/icl: add icelake_init_clock_gating()
 from Paulo Zanoni 
   - Squashed with this patch:
   drm/i915/icl: WaForceEnableNonCoherent
 from Oscar Mateo 
   - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
 applies to B0 as well.
   - WaPipeControlBefore3DStateSamplePattern WABB was being applied
 to ICL incorrectly.
v4:
   - Wrap the commit message
   - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/i915_drv.h  |  9 +++
  drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
  drivers/gpu/drm/i915/i915_reg.h  |  1 +
  drivers/gpu/drm/i915/intel_lrc.c |  2 ++
  drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
  drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
  drivers/gpu/drm/i915/intel_workarounds.c | 46 
  7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0286911..1dc157f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
  #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
  
+#define ICL_REVID_A0		0x0

+#define ICL_REVID_A2   0x1

Just noted that for some reason bspec puts A0 and A2 under
same revid. Bspec err?


That's what I hope. I have opened a bug against the BSpec to be 100% sure.


+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
  /*
   * The genX designation typically refers to the render engine, so render
   * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
  /* GEN8 chicken */
  #define HDC_CHICKEN0  _MMIO(0x7300)
  #define CNL_HDC_CHICKEN0  _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE   (1<<15)
  #define  HDC_FENCE_DEST_SLM_DISABLE   (1<<14)
  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED  (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a..2d6572a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
  
  	switch (INTEL_GEN(engine->i915)) {

+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..3b7d804 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private 
*d

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-26 Thread Mika Kuoppala 
Oscar Mateo  writes:

> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
>   - Since it has been fixed already in upstream, removed the TODO
> comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>   - Squashed with this patch:
>   drm/i915/icl: add icelake_init_clock_gating()
> from Paulo Zanoni 
>   - Squashed with this patch:
>   drm/i915/icl: WaForceEnableNonCoherent
> from Oscar Mateo 
>   - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
> applies to B0 as well.
>   - WaPipeControlBefore3DStateSamplePattern WABB was being applied
> to ICL incorrectly.
> v4:
>   - Wrap the commit message
>   - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
>
> Cc: Tomasz Lis 
> Cc: Mika Kuoppala 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  9 +++
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
>  drivers/gpu/drm/i915/intel_workarounds.c | 46 
> 
>  7 files changed, 68 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0286911..1dc157f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_CNL_REVID(p, since, until) \
>   (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>  
> +#define ICL_REVID_A0 0x0
> +#define ICL_REVID_A2 0x1

Just noted that for some reason bspec puts A0 and A2 under
same revid. Bspec err?

> +#define ICL_REVID_B0 0x3
> +#define ICL_REVID_B2 0x4
> +#define ICL_REVID_C0 0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> + (IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
>  /*
>   * The genX designation typically refers to the render engine, so render
>   * capability related checks should use IS_GEN, while display and other 
> checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 21d72f6..221b873 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
> drm_i915_private *dev_priv)
>* called on driver load and after a GPU reset, so you can place
>* workarounds here even if they get overwritten by GPU reset.
>*/
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>   if (IS_BROADWELL(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>   else if (IS_CHERRYVIEW(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
> IS_GEN11(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>   else if (IS_GEN9_LP(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..f2ee225 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7203,6 +7203,7 @@ enum {
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0 _MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> +#define ICL_HDC_CHICKEN0 _MMIO(0xE5F4)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE  (1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE  (1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 029901a..2d6572a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct 
> intel_engine_cs *engine)
>   return -EINVAL;
>  
>   switch (INTEL_GEN(engine->i915)) {
> + case 11:
> + return 0;
>   case 10:
>   wa_bb_fn[0] = gen10_init_indirectctx_bb;
>   wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4baab85..3b7d804 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(stru

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-20 Thread Oscar Mateo 
Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 
 7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0286911..1dc157f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a..2d6572a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..3b7d804 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_CANNONLAKE(dev_priv))
+   if (IS_ICELAKE(dev_priv))
+   dev_priv->display.init_clock_gating = nop_init_clock_gating;
+   else

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-13 Thread Oscar Mateo 
Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 47 
 6 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e50d958..b08a22a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c8513..675c19d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1633,6 +1633,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..cfa03ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,6 +9123,8 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
+   if (IS_ICELAKE(dev_priv))
+   dev_priv->display.init_clock_gating = nop_init_clock_gating;
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/d

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-09 Thread Oscar Mateo 



On 4/9/2018 12:53 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2018-04-06 23:24:57)

Inherit workarounds from previous platforms that are still valid for
Icelake.

Speaking of the workarounds, where do we stand with at least landing the
split out of init_workarounds_ring()?

Rebuilding the invariant wa_regs[] on every reset is annoying, and how
many of the general mmio need to be reemitted everytime? I would dearly
like to get the flow of the gt/context workarounds improved.
-Chris


I'm afraid we stand nowhere. The latest patches I sent were sidetracked 
by a conversation about where i915.rst should reside:


https://patchwork.freedesktop.org/patch/206937/
https://patchwork.freedesktop.org/patch/206557/

I can try once more, see if I am more lucky this time around?
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Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-09 Thread Chris Wilson 
Quoting Oscar Mateo (2018-04-06 23:24:57)
> Inherit workarounds from previous platforms that are still valid for
> Icelake.

Speaking of the workarounds, where do we stand with at least landing the
split out of init_workarounds_ring()?

Rebuilding the invariant wa_regs[] on every reset is annoying, and how
many of the general mmio need to be reemitted everytime? I would dearly
like to get the flow of the gt/context workarounds improved.
-Chris
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[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

2018-04-06 Thread Oscar Mateo 
Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h|  9 +
 drivers/gpu/drm/i915/i915_gem_gtt.c|  4 ++--
 drivers/gpu/drm/i915/i915_reg.h|  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +
 drivers/gpu/drm/i915/intel_lrc.c   |  2 ++
 drivers/gpu/drm/i915/intel_pm.c| 19 ++-
 6 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..1a4801e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2458,6 +2458,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6..6cd2f2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7184,6 +7184,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..ba8c137 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1467,6 +1467,29 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
return 0;
 }
 
+static int icl_init_workarounds(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+
+   /* Wa_1604370585:icl (pre-prod)
+* Formerly known as WaPushConstantDereferenceHoldDisable
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+   /* WaForceEnableNonCoherent:icl
+* This is not the same workaround as in early Gen9 platforms, where
+* lacking this could cause system hangs, but coherency performance
+* overhead is high and only a few compute workloads really need it
+* (the register is whitelisted in hardware now, so UMDs can opt in
+* for coherency if they have a good reason).
+*/
+   WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHEREN