[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-21 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_params
and skl_compute_plane_wm.
Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 +---
 3 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81ab25d..c64c846 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1471,6 +1471,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d5a6242..d2f58cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,6 +597,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1095e20..1545ead 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4419,7 +4419,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_id)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4432,6 +4432,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4439,6 +4445,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4451,7 +4458,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_id == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_id];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_id)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,19 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id intel_plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   ddb_blocks = plane_id ?
+skl_ddb_entry_size(>uv_plane[pipe][intel_plane_id]) :
+skl_ddb_entry_size(>plane[pipe][intel_plane_id]);

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-14 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_params
and skl_compute_plane_wm.
Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 +---
 3 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8967cc1..590e5f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1464,6 +1464,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f13decc..6402d6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3eeb66d..bfe64a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_id)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_id == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_id];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_id)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id intel_plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   ddb_blocks = plane_id ?
+skl_ddb_entry_size(>uv_plane[pipe][intel_plane_id]) :
+skl_ddb_entry_size(>plane[pipe][intel_plane_id]);

Re: [Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-14 Thread Sharma, Shashank 
Ideal case would have been an enum for nv12 planes with y and uv 
parameters, to indicate in code, but I will at least prefer the 
plane_num variable should be replaced by plane_id, as plane_number 0 and 
1 confuses.


With that change, feel free to use:

Reviewed-by: Shashank Sharma 

Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

Signed-off-by: Mahesh Kumar 
---
  drivers/gpu/drm/i915/i915_drv.h  |  1 +
  drivers/gpu/drm/i915/intel_drv.h |  1 +
  drivers/gpu/drm/i915/intel_pm.c  | 55 +++-
  3 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9914bb..9a9a645 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1463,6 +1463,7 @@ struct skl_wm_level {
  struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f13decc..6402d6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
  
  struct skl_plane_wm {

struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
  };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bc0e2bf..2a0cc0b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
  {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
  
+	/* only NV12 format has two planes */

+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
  
  	if (plane->id == PLANE_CURSOR) {

wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
  
-	wp->cpp = fb->format->cpp[0];

+   if (plane_num == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
  
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,

  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
  {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
  
  	if (WARN_ON(!intel_pstate->base.fb))

return -EINVAL;
  
-	ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);

+   ddb_blocks = plane_num ?
+skl_ddb_entry_size(>uv_plane[pipe][plane_id]) :
+

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-13 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 55 +++-
 3 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9914bb..9a9a645 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1463,6 +1463,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f13decc..6402d6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bc0e2bf..2a0cc0b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   ddb_blocks = plane_num ?
+skl_ddb_entry_size(>uv_plane[pipe][plane_id]) :
+skl_ddb_entry_size(>plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-13 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 +++-
 3 files changed, 44 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb339ec..b8e064c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1461,6 +1461,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4ebafdb..1f9fa87 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c525652..a77d572 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,18 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   ddb_blocks = plane_num ? 
skl_ddb_entry_size(>uv_plane[pipe][plane_id]) :
+
skl_ddb_entry_size(>plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];

Re: [Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-13 Thread Kumar, Mahesh 

Hi,


On 2/7/2018 10:12 PM, Sharma, Shashank wrote:

Regards

Shashank


On 2/6/2018 6:28 PM, Vidya Srinivas wrote:

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
  drivers/gpu/drm/i915/i915_drv.h  |  1 +
  drivers/gpu/drm/i915/intel_drv.h |  1 +
  drivers/gpu/drm/i915/intel_pm.c  | 54 


  3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h

index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
  struct skl_wm_params {
  bool x_tiled, y_tiled;
  bool rc_surface;
+    bool is_nv12;
  uint32_t width;
  uint8_t cpp;
  uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h 
b/drivers/gpu/drm/i915/intel_drv.h

index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
    struct skl_plane_wm {
  struct skl_wm_level wm[8];
+    struct skl_wm_level uv_wm[8];
  struct skl_wm_level trans_wm;
  bool is_nv12;
  };
diff --git a/drivers/gpu/drm/i915/intel_pm.c 
b/drivers/gpu/drm/i915/intel_pm.c

index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
-    struct skl_wm_params *wp)
+    struct skl_wm_params *wp, int plane_num)
Is this plane_num intended for 'no of planes' or 'plane number' ? from 
the usage below looks like 'no of planes' but I could be wrong.

it's plane-number.

  {
  struct intel_plane *plane = 
to_intel_plane(intel_pstate->base.plane);

  const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,

  if (!intel_wm_plane_visible(cstate, intel_pstate))
  return 0;
  +    /* only NV12 format has two planes */
+    if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+    DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+    return -EINVAL;
+    }
The comment says only NV12 format can have two planes, but if format 
!= NV12 && plane_num == 1, why is this an error ? Also the debug 
message says "Non NV12 format have single plane". Shouldn't it ?
Looks like you are expecting plane_number = 0, 1 for NV12 planes, and 
when plane_num is non-zero, you expect it to be NV12 only ?
yes, non-planar formats will have single plane, that's why if format != 
NV12 & plane_num == 1 it's an error.



+
  wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
    fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
    fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,

  wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
  wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
   fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+    wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
    if (plane->id == PLANE_CURSOR) {
  wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,

  wp->width = drm_rect_width(_pstate->base.src) >> 16;
  }
  -    wp->cpp = fb->format->cpp[0];
+    if (plane_num == 1 && wp->is_nv12)
+    wp->width /= 2;
+
+    wp->cpp = fb->format->cpp[plane_num];
  wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
   intel_pstate);
  @@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct 
drm_i915_private *dev_priv,

    struct intel_crtc_state *cstate,
    const struct intel_plane_state *intel_pstate,
    const struct skl_wm_params *wm_params,
-  struct skl_plane_wm *wm)
+  struct skl_plane_wm *wm,
+  int plane_num)

Same question here

  {
  struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
  struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct 
drm_i915_private *dev_priv,

  uint16_t ddb_blocks;
  enum pipe pipe = intel_crtc->pipe;
  int level, max_level = ilk_wm_max_level(dev_priv);
+    enum plane_id plane_id = intel_plane->id;
  int ret;
    if (WARN_ON(!intel_pstate->base.fb))
  return -EINVAL;
  -    ddb_blocks = 
skl_ddb_entry_size(>plane[pipe][intel_plane->id]);

+    if (plane_num == 0)
+   

Re: [Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-07 Thread Sharma, Shashank 

Regards

Shashank


On 2/6/2018 6:28 PM, Vidya Srinivas wrote:

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
  drivers/gpu/drm/i915/i915_drv.h  |  1 +
  drivers/gpu/drm/i915/intel_drv.h |  1 +
  drivers/gpu/drm/i915/intel_pm.c  | 54 
  3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
  struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
  
  struct skl_plane_wm {

struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
  };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
Is this plane_num intended for 'no of planes' or 'plane number' ? from 
the usage below looks like 'no of planes' but I could be wrong.

  {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
  
+	/* only NV12 format has two planes */

+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
The comment says only NV12 format can have two planes, but if format != 
NV12 && plane_num == 1, why is this an error ? Also the debug message 
says "Non NV12 format have single plane". Shouldn't it ?
Looks like you are expecting plane_number = 0, 1 for NV12 planes, and 
when plane_num is non-zero, you expect it to be NV12 only ?

+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
  
  	if (plane->id == PLANE_CURSOR) {

wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
  
-	wp->cpp = fb->format->cpp[0];

+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
  
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,

  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)

Same question here

  {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
  
  	if (WARN_ON(!intel_pstate->base.fb))

return -EINVAL;
  
-	ddb_blocks =

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-06 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   if (plane_num == 0)
+   ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
+   else
+   ddb_blocks = skl_ddb_entry_size(>uv_plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-02-06 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   if (plane_num == 0)
+   ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
+   else
+   ddb_blocks = skl_ddb_entry_size(>uv_plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

2018-01-22 Thread Vidya Srinivas 
From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df91904..c7abe91 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1452,6 +1452,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8473434..7644ca7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -591,6 +591,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e790679..f79787b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4413,7 +4413,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4426,6 +4426,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4433,6 +4439,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4445,7 +4452,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4606,7 +4616,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4614,15 +4625,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   if (plane_num == 0)
+   ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
+   else
+   ddb_blocks = skl_ddb_entry_size(>uv_plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,