[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

2018-05-08 Thread Oscar Mateo 
Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
  - Added References (Mika)
  - Rebased
v5:
  - Rebased
  - C, not lisp (Chris)
  - Correct reference number (Mika)

References: HSDES#220160670
Signed-off-by: Oscar Mateo 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1a8c..7fe505c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8263,6 +8263,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3b03729..2561c55 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   (I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
   GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  (I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+  GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

2018-05-04 Thread Mika Kuoppala 
Oscar Mateo  writes:

> Adjust default GAM TLB partitioning for performance reasons.
>
> v2: Only touch the bits that we really need
> v3: Rebased on top of the WA refactoring
> v4:
>   - Added References (Mika)
>   - Rebased
>
> References: HSDES#220260670
s/220260670/220160670

> Cc: Mika Kuoppala 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 5 +
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62c4fd2..a132980 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8263,6 +8263,11 @@ enum {
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN   _MMIO(0x9550)
>  #define   DFR_DISABLE(1 << 9)
>  
> +#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
> +#define   GEN11_HASH_CTRL_MASK   (0x3 << 12 | 0xf << 0)
> +#define   GEN11_HASH_CTRL_BIT0   (1 << 0)
> +#define   GEN11_HASH_CTRL_BIT4   (1 << 12)

Bspec only mentions that we should choose from group C, without
saying which hash to choose. And this is from group C.

Reviewed-by: Mika Kuoppala 

> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)   _MMIO(0xB008 + (slice) * 0x200) 
> /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK   (0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 93591a0..2bb5dad 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(GEN11_GLBLINVL,
>  ((I915_READ(GEN11_GLBLINVL) & 
> ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
>   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
> +
> + /* WaModifyGamTlbPartitioning:icl */
> + I915_WRITE(GEN11_GACB_PERF_CTRL,
> +((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
> + GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

2018-05-02 Thread Oscar Mateo 
Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
  - Added References (Mika)
  - Rebased

References: HSDES#220260670
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62c4fd2..a132980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8263,6 +8263,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 93591a0..2bb5dad 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

2018-04-20 Thread Oscar Mateo 
Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 83a53cc..e8d14a7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

2018-04-13 Thread Oscar Mateo 
Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a94cd93..d7b2b07 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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