Re: [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll

2023-04-28 Thread Andi Shyti 
Hi Mika,

On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.

if you will resend it:

/Enabling/Enable/

Andi

Re: [Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll

2023-04-25 Thread Radhakrishna Sripada 
On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.
> 
Bspec: 64568

> Signed-off-by: Mika Kahola 
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h |   7 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c |   4 +-
>  3 files changed, 138 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 4231ba98f075..9722d3f1b926 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2600,8 +2600,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
>   return val;
>  }
>  
> -void intel_cx0pll_enable(struct intel_encoder *encoder,
> -  const struct intel_crtc_state *crtc_state)
> +static void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>   enum phy phy = intel_port_to_phy(i915, encoder->port);
> @@ -2676,7 +2676,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
>   intel_cx0_phy_transaction_end(encoder, wakeref);
>  }
>  
> -void intel_cx0pll_disable(struct intel_encoder *encoder)
> +static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int 
> clock)
> +{
> + switch (clock) {
> + case 162000:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> + case 27:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_270;
> + case 54:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_540;
> + case 81:
> + return XELPDP_DDI_CLOCK_SELECT_TBT_810;
> + default:
> + MISSING_CASE(clock);
> + return XELPDP_DDI_CLOCK_SELECT_TBT_162;
> + }
> +}
> +
> +static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> +  const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + u32 val = 0;
> +
> + /*
> +  * 1. Program PORT_CLOCK_CTL REGISTER to configure
> +  * clock muxes, gating and SSC
> +  */
> + val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, 
> crtc_state->port_clock));
> + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> +  XELPDP_DDI_CLOCK_SELECT_MASK | 
> XELPDP_FORWARD_CLOCK_UNGATE, val);
> +
> + /* 2. Read back PORT_CLOCK_CTL REGISTER */
> + val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +
> + /*
> +  * 3. Follow the Display Voltage Frequency Switching - Sequence
> +  * Before Frequency Change. We handle this step in bxt_set_cdclk().
> +  */
> +
> + /*
> +  * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable 
> PLL.
> +  */
> + val |= XELPDP_TBT_CLOCK_REQUEST;
> + intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> +
> + /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> + if (__intel_wait_for_register(>uncore, 
> XELPDP_PORT_CLOCK_CTL(encoder->port),
intel_de_wait_for_register can be used here.

> +   XELPDP_TBT_CLOCK_ACK,
> +   XELPDP_TBT_CLOCK_ACK,
> +   100, 0, NULL))
> + drm_warn(>drm, "[ENCODER:%d:%s][%c] PHY PLL not locked 
> after 100us.\n",
> +  encoder->base.base.id, encoder->base.name, 
> phy_name(phy));
> +
> + /*
> +  * 6. Follow the Display Voltage Frequency Switching Sequence After
> +  * Frequency Change. We handle this step in bxt_set_cdclk().
> +  */
> +
> + /*
> +  * 7. Program DDI_CLK_VALFREQ to match intended DDI
> +  * clock frequency.
> +  */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> +crtc_state->port_clock);
> +}
> +
> +void intel_mtl_pll_enable(struct intel_encoder *encoder,
> +   const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + intel_mtl_tbt_pll_enable(encoder, crtc_state);
> + else
> + intel_cx0pll_enable(encoder, crtc_state);
> +}
> +
> +static void intel_cx0pll_disable(struct intel_encoder *encoder)
>  {
>   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>   enum phy phy = intel_port_to_phy(i915, encoder->port);
> @@ -2728,6 +2807,56 @@ void intel_cx0pll_disable(struct intel_encoder 
> *encoder)
>   intel_cx0_phy_transaction_end(encoder, wakeref);
>  }
>  
> +static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> +{
>

[Intel-gfx] [PATCH 07/13] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll

2023-04-20 Thread Mika Kahola 
Enabling and disabling sequence for Thunderbolt PLL.

Signed-off-by: Mika Kahola 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |   7 +-
 drivers/gpu/drm/i915/display/intel_ddi.c |   4 +-
 3 files changed, 138 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4231ba98f075..9722d3f1b926 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2600,8 +2600,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
return val;
 }
 
-void intel_cx0pll_enable(struct intel_encoder *encoder,
-const struct intel_crtc_state *crtc_state)
+static void intel_cx0pll_enable(struct intel_encoder *encoder,
+   const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2676,7 +2676,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
-void intel_cx0pll_disable(struct intel_encoder *encoder)
+static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+{
+   switch (clock) {
+   case 162000:
+   return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+   case 27:
+   return XELPDP_DDI_CLOCK_SELECT_TBT_270;
+   case 54:
+   return XELPDP_DDI_CLOCK_SELECT_TBT_540;
+   case 81:
+   return XELPDP_DDI_CLOCK_SELECT_TBT_810;
+   default:
+   MISSING_CASE(clock);
+   return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+   }
+}
+
+static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum phy phy = intel_port_to_phy(i915, encoder->port);
+   u32 val = 0;
+
+   /*
+* 1. Program PORT_CLOCK_CTL REGISTER to configure
+* clock muxes, gating and SSC
+*/
+   val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, 
crtc_state->port_clock));
+   val |= XELPDP_FORWARD_CLOCK_UNGATE;
+   intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+XELPDP_DDI_CLOCK_SELECT_MASK | 
XELPDP_FORWARD_CLOCK_UNGATE, val);
+
+   /* 2. Read back PORT_CLOCK_CTL REGISTER */
+   val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+
+   /*
+* 3. Follow the Display Voltage Frequency Switching - Sequence
+* Before Frequency Change. We handle this step in bxt_set_cdclk().
+*/
+
+   /*
+* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable 
PLL.
+*/
+   val |= XELPDP_TBT_CLOCK_REQUEST;
+   intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+
+   /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
+   if (__intel_wait_for_register(>uncore, 
XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_ACK,
+ XELPDP_TBT_CLOCK_ACK,
+ 100, 0, NULL))
+   drm_warn(>drm, "[ENCODER:%d:%s][%c] PHY PLL not locked 
after 100us.\n",
+encoder->base.base.id, encoder->base.name, 
phy_name(phy));
+
+   /*
+* 6. Follow the Display Voltage Frequency Switching Sequence After
+* Frequency Change. We handle this step in bxt_set_cdclk().
+*/
+
+   /*
+* 7. Program DDI_CLK_VALFREQ to match intended DDI
+* clock frequency.
+*/
+   intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+  crtc_state->port_clock);
+}
+
+void intel_mtl_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+   if (intel_tc_port_in_tbt_alt_mode(dig_port))
+   intel_mtl_tbt_pll_enable(encoder, crtc_state);
+   else
+   intel_cx0pll_enable(encoder, crtc_state);
+}
+
+static void intel_cx0pll_disable(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2728,6 +2807,56 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
+static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+   /*
+* 1. Follow the Display Voltage Frequency Switching Sequence Before
+* Frequency