Re: [Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

2017-10-27 Thread Jani Nikula
On Thu, 26 Oct 2017, "Pandiyan, Dhinakaran" wrote: > On Thu, 2017-10-26 at 10:59 +0300, Jani Nikula wrote: >> On Thu, 10 Aug 2017, Dhinakaran Pandiyan wrote: >> > DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state >> > >> > 101 = Set Main-Link for local Sink device and all downstream

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

2017-10-26 Thread Pandiyan, Dhinakaran
On Thu, 2017-10-26 at 10:59 +0300, Jani Nikula wrote: > On Thu, 10 Aug 2017, Dhinakaran Pandiyan wrote: > > DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state > > > > 101 = Set Main-Link for local Sink device and all downstream Sink > > devices to D3 (power-down mode), keep AUX block

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

2017-10-26 Thread Jani Nikula
On Thu, 10 Aug 2017, Dhinakaran Pandiyan wrote: > DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state > > 101 = Set Main-Link for local Sink device and all downstream Sink > devices to D3 (power-down mode), keep AUX block fully powered, ready to > reply within a Response Timeout period

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

2017-08-10 Thread Jani Nikula
On Fri, 11 Aug 2017, Dhinakaran Pandiyan wrote: > DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state > > 101 = Set Main-Link for local Sink device and all downstream Sink > devices to D3 (power-down mode), keep AUX block fully powered, ready to > reply within a Response Timeout period

[Intel-gfx] [PATCH 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

2017-08-10 Thread Dhinakaran Pandiyan
DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state 101 = Set Main-Link for local Sink device and all downstream Sink devices to D3 (power-down mode), keep AUX block fully powered, ready to reply within a Response Timeout period of 300us. This state is useful in a MST dock + MST monito