Re: [Intel-gfx] [PATCH 15/17] drm/i915/display: switch to kernel types
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 104 +--
>
> 1 file changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index af164d712e9e..b3d6ee7eee0e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -49,7 +49,7 @@
> #include
>
> /* Primary plane formats for gen <= 3 */
> -static const uint32_t i8xx_primary_formats[] = {
> +static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
> @@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = {
> };
>
> /* Primary plane formats for gen >= 4 */
> -static const uint32_t i965_primary_formats[] = {
> +static const u32 i965_primary_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB,
> @@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = {
> DRM_FORMAT_XBGR2101010,
> };
>
> -static const uint64_t i9xx_format_modifiers[] = {
> +static const u64 i9xx_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> DRM_FORMAT_MOD_INVALID
> };
>
> /* Cursor formats */
> -static const uint32_t intel_cursor_formats[] = {
> +static const u32 intel_cursor_formats[] = {
> DRM_FORMAT_ARGB,
> };
>
> -static const uint64_t cursor_format_modifiers[] = {
> +static const u64 cursor_format_modifiers[] = {
> DRM_FORMAT_MOD_LINEAR,
> DRM_FORMAT_MOD_INVALID
> };
> @@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk,
> struct dpll *clock)
> return clock->dot;
> }
>
> -static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
> +static u32 i9xx_dpll_compute_m(struct dpll *dpll)
> {
> return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
> }
> @@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll
> *clock)
> clock->p = clock->p1 * clock->p2;
> if (WARN_ON(clock->n == 0 || clock->p == 0))
> return 0;
> - clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
> - clock->n << 22);
> + clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
> +clock->n << 22);
> clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
>
> return clock->dot / 5;
> @@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit
> *limit,
> struct drm_device *dev = crtc->base.dev;
> unsigned int best_error_ppm;
> struct dpll clock;
> - uint64_t m2;
> + u64 m2;
> int found = false;
>
> memset(best_clock, 0, sizeof(*best_clock));
> @@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit
> *limit,
>
> clock.p = clock.p1 * clock.p2;
>
> - m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target *
> clock.p *
> + m2 = DIV_ROUND_CLOSEST_ULL(((u64)target *
> clock.p *
> clock.n) << 22, refclk *
> clock.m1);
>
> if (m2 > INT_MAX/clock.m1)
> @@ -1610,7 +1610,7 @@ static void
> ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> - uint32_t val, pipeconf_val;
> + u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> @@ -1698,7 +1698,7 @@ static void
> ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> i915_reg_t reg;
> - uint32_t val;
> + u32 val;
>
> /* FDI relies on the transcoder */
> assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int
> *y,
> return 0;
> }
>
> -static unsigned int intel_fb_modifier_to_tiling(uint64_t
> fb_modifier)
> +static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> {
> switch (fb_modifier) {
> case I915_FORMAT_MOD_X_TILED:
> @@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct
> intel_plane_state *plane_state,
> return stride / skl_plane_stride_mult(fb, color_plane,
> rotation);
> }
>
> -static u32 skl_plane_ctl_format(uint32_t pixel_format)
> +static u32 skl_plane_ctl_format(u32 pixel_format)
> {
> switch (pixel_format) {
> case DRM_FORMAT_C8:
> @@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const
> struct intel_plane_state *plane_state
> }
> }
>
> -static u32 skl_plane_ctl_tiling(uint64_t
[Intel-gfx] [PATCH 15/17] drm/i915/display: switch to kernel types
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 104 +--
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index af164d712e9e..b3d6ee7eee0e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -49,7 +49,7 @@
#include
/* Primary plane formats for gen <= 3 */
-static const uint32_t i8xx_primary_formats[] = {
+static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB1555,
@@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = {
};
/* Primary plane formats for gen >= 4 */
-static const uint32_t i965_primary_formats[] = {
+static const u32 i965_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB,
@@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
-static const uint64_t i9xx_format_modifiers[] = {
+static const u64 i9xx_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID
};
/* Cursor formats */
-static const uint32_t intel_cursor_formats[] = {
+static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
};
-static const uint64_t cursor_format_modifiers[] = {
+static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID
};
@@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk, struct dpll
*clock)
return clock->dot;
}
-static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
+static u32 i9xx_dpll_compute_m(struct dpll *dpll)
{
return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}
@@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
clock->p = clock->p1 * clock->p2;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
- clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
- clock->n << 22);
+ clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
+ clock->n << 22);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot / 5;
@@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
struct drm_device *dev = crtc->base.dev;
unsigned int best_error_ppm;
struct dpll clock;
- uint64_t m2;
+ u64 m2;
int found = false;
memset(best_clock, 0, sizeof(*best_clock));
@@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
clock.p = clock.p1 * clock.p2;
- m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
+ m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *
clock.n) << 22, refclk * clock.m1);
if (m2 > INT_MAX/clock.m1)
@@ -1610,7 +1610,7 @@ static void ironlake_enable_pch_transcoder(const struct
intel_crtc_state *crtc_s
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
- uint32_t val, pipeconf_val;
+ u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
@@ -1698,7 +1698,7 @@ static void ironlake_disable_pch_transcoder(struct
drm_i915_private *dev_priv,
enum pipe pipe)
{
i915_reg_t reg;
- uint32_t val;
+ u32 val;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
@@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
return 0;
}
-static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
+static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
switch (fb_modifier) {
case I915_FORMAT_MOD_X_TILED:
@@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct intel_plane_state
*plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
-static u32 skl_plane_ctl_format(uint32_t pixel_format)
+static u32 skl_plane_ctl_format(u32 pixel_format)
{
switch (pixel_format) {
case DRM_FORMAT_C8:
@@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const struct
intel_plane_state *plane_state
}
}
-static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
+static u32 skl_plane_ctl_tiling(u64 fb_modifier)
{
switch (fb_modifier) {
case DRM_FORMAT_MOD_LINEAR:
@@ -4597,7 +4597,7 @@ static void ironlake_pch_transcoder_set_timings(const
struct intel_crtc_state *c
static void
