[Intel-gfx] [PATCH 2/2] drm/i915: Split out functions for different kinds of workarounds

[Oscar Mateo]

There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
be easier to decide where a new workaround should go.

v2:
  - Add multiple MISSING_CASE
  - Rebased

v3:
  - Rename mmio_workarounds to gt_workarounds (Chris, Mika)
  - Create empty placeholders for BDW and CHV GT WAs
  - Rebased

v4: Rebased

v5:
  - Rebased
  - FORCE_TO_NONPRIV register exists since BDW, so make a path
for it to achieve universality, even if empty (Chris)

v6:
  - Rebased
  - A few stylistic changes to please checkpatch and sparse

Signed-off-by: Oscar Mateo 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c  |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |   6 +
 drivers/gpu/drm/i915/intel_lrc.c |  14 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   8 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 637 ---
 drivers/gpu/drm/i915/intel_workarounds.h |   8 +-
 6 files changed, 438 insertions(+), 238 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28ab0be..ab846f8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
 #include "intel_mocs.h"
+#include "intel_workarounds.h"
 #include "i915_gemfs.h"
 #include 
 #include 
@@ -5198,6 +5199,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
 
+   intel_gt_workarounds_apply(dev_priv);
+
i915_gem_init_swizzling(dev_priv);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5cfac02..9b3834a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_workarounds.h"
 
 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
 
@@ -459,11 +460,16 @@ static bool needs_preempt_context(struct drm_i915_private 
*i915)
 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 {
struct i915_gem_context *ctx;
+   int ret;
 
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
 
+   ret = intel_ctx_workarounds_init(dev_priv);
+   if (ret)
+   return ret;
+
INIT_LIST_HEAD(_priv->contexts.list);
INIT_WORK(_priv->contexts.free_work, contexts_free_worker);
init_llist_head(_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c250c8b..568a59b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1725,6 +1725,10 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
/* We need to disable the AsyncFlip performance optimisations in order
 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 * programmed to '1' on all products.
@@ -1735,7 +1739,7 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
 
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1746,7 +1750,11 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   return init_workarounds_ring(engine);
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void reset_common_ring(struct intel_engine_cs *engine,
@@ -2071,7 +2079,7 @@ static int gen8_init_rcs_context(struct i915_request *rq)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(rq);
+   ret = intel_ctx_workarounds_emit(rq);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 36acc32..757bb09 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,7 +600,7 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(rq);
+   ret = intel_ctx_workarounds_emit(rq);
if (ret != 0)
return ret;
 
@@ -618,6 +618,10 @@ static int 

[Intel-gfx] [PATCH 2/2] drm/i915: Split out functions for different kinds of workarounds

[Oscar Mateo]

There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
be easier to decide where a new workaround should go.

v2:
  - Add multiple MISSING_CASE
  - Rebased

v3:
  - Rename mmio_workarounds to gt_workarounds (Chris, Mika)
  - Create empty placeholders for BDW and CHV GT WAs
  - Rebased

v4: Rebased

v5:
 - Rebased
 - FORCE_TO_NONPRIV register exists since BDW, so make a path
   for it to achieve universality, even if empty (Chris)

Signed-off-by: Oscar Mateo 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c  |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |   6 +
 drivers/gpu/drm/i915/intel_lrc.c |  14 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   8 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 636 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   8 +-
 6 files changed, 433 insertions(+), 242 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28ab0be..ab846f8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
 #include "intel_mocs.h"
+#include "intel_workarounds.h"
 #include "i915_gemfs.h"
 #include 
 #include 
@@ -5198,6 +5199,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
 
+   intel_gt_workarounds_apply(dev_priv);
+
i915_gem_init_swizzling(dev_priv);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5cfac02..9b3834a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_workarounds.h"
 
 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
 
@@ -459,11 +460,16 @@ static bool needs_preempt_context(struct drm_i915_private 
*i915)
 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 {
struct i915_gem_context *ctx;
+   int ret;
 
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
 
+   ret = intel_ctx_workarounds_init(dev_priv);
+   if (ret)
+   return ret;
+
INIT_LIST_HEAD(_priv->contexts.list);
INIT_WORK(_priv->contexts.free_work, contexts_free_worker);
init_llist_head(_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c250c8b..568a59b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1725,6 +1725,10 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
/* We need to disable the AsyncFlip performance optimisations in order
 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 * programmed to '1' on all products.
@@ -1735,7 +1739,7 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
 
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1746,7 +1750,11 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   return init_workarounds_ring(engine);
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void reset_common_ring(struct intel_engine_cs *engine,
@@ -2071,7 +2079,7 @@ static int gen8_init_rcs_context(struct i915_request *rq)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(rq);
+   ret = intel_ctx_workarounds_emit(rq);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 36acc32..757bb09 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,7 +600,7 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(rq);
+   ret = intel_ctx_workarounds_emit(rq);
if (ret != 0)
return ret;
 
@@ -618,6 +618,10 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (ret)
return ret;
 
+