Re: [Intel-gfx] [PATCH 4/6] drm/i915/icl: Enhanced execution list support

2018-03-07 Thread Chris Wilson 
Quoting Mika Kuoppala (2018-03-02 16:14:59)
> From: Thomas Daniel 
> 
> Enhanced Execlists is an upgraded version of execlists which supports
> up to 8 ports. The lrcs to be submitted are written to a submit queue
> (the ExecLists Submission Queue - ELSQ), which is then loaded on the
> HW. When writing to the ELSP register, the lrcs are written cyclically
> in the queue from position 0 to position 7. Alternatively, it is
> possible to write directly in the individual positions of the queue
> using the ELSQC registers. To be able to re-use all the existing code
> we're using the latter method and we're currently limiting ourself to
> only using 2 elements.
> 
> v2: Rebase.
> v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
> v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
> v5: Reword commit, rename regs to be closer to specs, turn off
> preemption (Daniele), reuse engine->execlists.elsp (Chris)
> v6: use has_logical_ring_elsq to differentiate the new paths
> v7: add preemption support, rename els to submit_reg (Chris)
> v8: save the ctrl register inside the execlists struct, drop CSB
> handling updates (superseded by preempt_complete_status) (Chris)
> v9: s/drm_i915_gem_request/i915_request (Mika)
> v10: resolved conflict in inject_preempt_context (Mika)
> 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> Signed-off-by: Thomas Daniel 
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: Daniele Ceraolo Spurio 
> Reviewed-by: Chris Wilson  (v8)
Reviewed-by: Chris Wilson 
> Signed-off-by: Mika Kuoppala 
-Chris
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[Intel-gfx] [PATCH 4/6] drm/i915/icl: Enhanced execution list support

2018-03-02 Thread Mika Kuoppala 
From: Thomas Daniel 

Enhanced Execlists is an upgraded version of execlists which supports
up to 8 ports. The lrcs to be submitted are written to a submit queue
(the ExecLists Submission Queue - ELSQ), which is then loaded on the
HW. When writing to the ELSP register, the lrcs are written cyclically
in the queue from position 0 to position 7. Alternatively, it is
possible to write directly in the individual positions of the queue
using the ELSQC registers. To be able to re-use all the existing code
we're using the latter method and we're currently limiting ourself to
only using 2 elements.

v2: Rebase.
v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
v5: Reword commit, rename regs to be closer to specs, turn off
preemption (Daniele), reuse engine->execlists.elsp (Chris)
v6: use has_logical_ring_elsq to differentiate the new paths
v7: add preemption support, rename els to submit_reg (Chris)
v8: save the ctrl register inside the execlists struct, drop CSB
handling updates (superseded by preempt_complete_status) (Chris)
v9: s/drm_i915_gem_request/i915_request (Mika)
v10: resolved conflict in inject_preempt_context (Mika)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Thomas Daniel 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Chris Wilson  (v8)
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  |  3 +-
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 58 
 drivers/gpu/drm/i915/intel_lrc.h |  3 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 12 +--
 6 files changed, 62 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e2e6585549d..2b52592b193e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2772,6 +2772,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
((dev_priv)->info.has_logical_ring_contexts)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
+   ((dev_priv)->info.has_logical_ring_elsq)
 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
((dev_priv)->info.has_logical_ring_preemption)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26e8f5c13231..062e91b39085 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -594,7 +594,8 @@ static const struct intel_device_info intel_cannonlake_info 
= {
GEN10_FEATURES, \
GEN(11), \
.ddb_size = 2048, \
-   .has_csr = 0
+   .has_csr = 0, \
+   .has_logical_ring_elsq = 1
 
 static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index ab5bfd305477..7cc5a8e649b5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -96,6 +96,7 @@ enum intel_platform {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+   func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_pooled_eu); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e50d86af1345..ea88e74ba8ac 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -417,18 +417,30 @@ static u64 execlists_update_context(struct i915_request 
*rq)
return ce->lrc_desc;
 }
 
-static inline void elsp_write(u64 desc, u32 __iomem *elsp)
+static inline void write_desc(struct intel_engine_execlists *execlists, u64 
desc, u32 port)
 {
-   writel(upper_32_bits(desc), elsp);
-   writel(lower_32_bits(desc), elsp);
+   if (execlists->ctrl_reg) {
+   writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
+   writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 
1);
+   } else {
+   writel(upper_32_bits(desc), execlists->submit_reg);
+   writel(lower_32_bits(desc), execlists->submit_reg);
+   }
 }
 
 static void execlists_submit_ports(struct intel_engine_cs *engine)
 {
-   struct execlist_port *port = engine->execlists.port;
+   struct intel_engine_execlists *execlists = >execlists;
+   struct execlist_port *port = execlists->port;
unsigned int n;
 
-   for (n = execlists_num_ports(>execlists); n--; ) {
+   /*
+* ELSQ note: the submit queue is not cleared after