[Intel-gfx] [PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Paulo Zanoni]

From: Mahesh Kumar 

This patch program default values of MBus credit during pipe enable.

Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase
Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes since V3 (from Paulo):
 - Remove WARN() that we'll never be able to trigger (Ville).

Cc: Ville Syrjälä 
Reviewed-by: Paulo Zanoni 
Reviewed-by: James Ausmus 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ad8d9c6c40e4..5a75bc1eafbc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5418,6 +5418,20 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
drm_i915_private *dev_priv,
I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 }
 
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe;
+   uint32_t val;
+
+   val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+   /* Program B credit equally to all pipes */
+   val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+   I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct drm_atomic_state *old_state)
 {
@@ -5495,6 +5509,9 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(old_intel_state, 
pipe_config);
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   icl_pipe_mbus_enable(intel_crtc);
+
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
intel_enable_pipe(pipe_config);
-- 
2.14.3

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Re: [Intel-gfx] [PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Ville Syrjälä]

On Mon, Feb 05, 2018 at 01:40:46PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> This patch program default values of MBus credit during pipe enable.
> 
> Changes since V2:
>  - We don't need to do anything when disabling the pipe
> Changes Since V1:
>  - Add WARN_ON (Paulo)
>  - Remove TODO comment
>  - Program 0 during pipe disable
>  - Rebase
> 
> Reviewed-by: Paulo Zanoni 
> Reviewed-by: James Ausmus 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index ad8d9c6c40e4..c5de5fe4e0dd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5418,6 +5418,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
> drm_i915_private *dev_priv,
>   I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
>  }
>  
> +static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + uint32_t val;
> +
> + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> + return;

That's clearly impossible. IMO these sort of super paranoid checks
are just adding noise to the code, making it harder to follow as you
may start to question your own sanity on account of not being able
to figure out how it could ever happen.

> +
> + val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
> +
> + /* Program B credit equally to all pipes */
> + val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
> +
> + I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> +}
> +
>  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>   struct drm_atomic_state *old_state)
>  {
> @@ -5495,6 +5512,9 @@ static void haswell_crtc_enable(struct intel_crtc_state 
> *pipe_config,
>   if (dev_priv->display.initial_watermarks != NULL)
>   dev_priv->display.initial_watermarks(old_intel_state, 
> pipe_config);
>  
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_pipe_mbus_enable(intel_crtc);
> +
>   /* XXX: Do the pipe assertions at the right place for BXT DSI. */
>   if (!transcoder_is_dsi(cpu_transcoder))
>   intel_enable_pipe(pipe_config);
> -- 
> 2.14.3
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 6/6] drm/i915/icl: program mbus during pipe enable

[Paulo Zanoni]

From: Mahesh Kumar 

This patch program default values of MBus credit during pipe enable.

Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase

Reviewed-by: Paulo Zanoni 
Reviewed-by: James Ausmus 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ad8d9c6c40e4..c5de5fe4e0dd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5418,6 +5418,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
drm_i915_private *dev_priv,
I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 }
 
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe;
+   uint32_t val;
+
+   if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+   return;
+
+   val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+   /* Program B credit equally to all pipes */
+   val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+   I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct drm_atomic_state *old_state)
 {
@@ -5495,6 +5512,9 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(old_intel_state, 
pipe_config);
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   icl_pipe_mbus_enable(intel_crtc);
+
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
intel_enable_pipe(pipe_config);
-- 
2.14.3

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