Since the aliasing-ppgtt remains the default for gen6/gen7, it is worth
optimising the ppgtt allocation for it. In this case, we do not need to
flush the GGTT page directories entries as they are fixed during setup.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1c1e807f674d..277737e2d41a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -184,12 +184,10 @@ static void gen6_alloc_va_range(struct i915_address_space
*vm,
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
struct i915_page_directory * const pd = ppgtt->base.pd;
struct i915_page_table *pt;
- intel_wakeref_t wakeref;
+ bool flush = false;
u64 from = start;
unsigned int pde;
- wakeref = intel_runtime_pm_get(>i915->runtime_pm);
-
spin_lock(>lock);
gen6_for_each_pde(pt, pd, start, length, pde) {
const unsigned int count = gen6_pte_count(start, length);
@@ -211,16 +209,20 @@ static void gen6_alloc_va_range(struct i915_address_space
*vm,
} else {
pt = pd->entry[pde];
}
+
+ flush = true;
}
atomic_add(count, >used);
}
spin_unlock(>lock);
- if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND))
- gen6_flush_pd(ppgtt, from, start);
+ if (flush && i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
+ intel_wakeref_t wakeref;
- intel_runtime_pm_put(>i915->runtime_pm, wakeref);
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref)
+ gen6_flush_pd(ppgtt, from, start);
+ }
}
static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt)
--
2.20.1
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