On Tue, Mar 13, 2018 at 12:58:59AM +, Souza, Jose wrote:
> On Mon, 2018-03-12 at 16:19 -0700, Pandiyan, Dhinakaran wrote:
> > On Mon, 2018-03-12 at 23:16 +, Souza, Jose wrote:
> > > What if FBC is disabled? Or FBC can not be activate by any of the
> > > reasons in intel_fbc_can_activate().
On Mon, 2018-03-12 at 16:19 -0700, Pandiyan, Dhinakaran wrote:
> On Mon, 2018-03-12 at 23:16 +, Souza, Jose wrote:
> > What if FBC is disabled? Or FBC can not be activate by any of the
> > reasons in intel_fbc_can_activate(). The hardware tracking would
> > never
> > trigger a PSR exit by it se
On Mon, 2018-03-12 at 23:16 +, Souza, Jose wrote:
> What if FBC is disabled? Or FBC can not be activate by any of the
> reasons in intel_fbc_can_activate(). The hardware tracking would never
> trigger a PSR exit by it self?!
>
Only frontbuffer tracking is tied to FBC, PSR exit on plane/pipe
What if FBC is disabled? Or FBC can not be activate by any of the
reasons in intel_fbc_can_activate(). The hardware tracking would never
trigger a PSR exit by it self?!
On Tue, 2018-03-06 at 19:34 -0800, Dhinakaran Pandiyan wrote:
> From: Rodrigo Vivi
>
> So far we are using frontbuffer tracking
From: Rodrigo Vivi
So far we are using frontbuffer tracking for everything
and ignoring that PSR has a HW capable HW tracking for many
modern usages of GPU on Core platforms and newer Atom ones.
One reason for that is that we were trying to keep same
infrastructure in place for VLV/CHV than the
