Re: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Lucas De Marchi
> Sent: Friday, August 23, 2019 1:21 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vetter, Daniel ; Pandiyan, Dhinakaran
>
> Subject: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render
> decompression
>
> From: Dhinakaran Pandiyan
>
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a ratio
> of
> 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
>
> Bspec: 18437
>
> v2: Fix checkpatch warnings (Lucas)
>
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 63 +---
> drivers/gpu/drm/i915/display/intel_sprite.c | 23 ---
> 2 files changed, 71 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> if (color_plane == 1)
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + if (color_plane == 1)
> + return cpp;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return 4 * 4 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>
> static bool is_surface_linear(u64 modifier, int color_plane) {
> - return modifier == DRM_FORMAT_MOD_LINEAR;
> + return modifier == DRM_FORMAT_MOD_LINEAR ||
> +(modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> +color_plane == 1);
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y, @@ -2429,6 +2436,7
> @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> return I915_TILING_X;
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
Shouldn’t this modifier be added to skl_max_plane_width as well?
Thanks,
Radhakrishna Sripada
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> * us a ratio of one byte in the CCS for each 8x16 pixels in the
> * main surface.
> */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
> { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[]
> = {
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair
> +in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> +Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having
> +dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> +pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1,
Re: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression
On Fri, Aug 23, 2019 at 01:20:53AM -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan
>
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
>
> Bspec: 18437
For TGL I think you want to point at bspec #49252.
>
> v2: Fix checkpatch warnings (Lucas)
>
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 63 +---
> drivers/gpu/drm/i915/display/intel_sprite.c | 23 ---
> 2 files changed, 71 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> if (color_plane == 1)
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + if (color_plane == 1)
> + return cpp;
If the CCS itself is linear, is there a reason we don't treat this the
way we normally treat linear surfaces (i.e., return intel_tile_size())?
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return 4 * 4 * 1024;
This is correct, but is there a reason we don't just write it as 16 *
1024? The bspec says "must be 16KB aligned" so 16 * 1024 seems more
natural.
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>
> static bool is_surface_linear(u64 modifier, int color_plane)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR;
> + return modifier == DRM_FORMAT_MOD_LINEAR ||
> +(modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
> == 1);
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2429,6 +2436,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> return I915_TILING_X;
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> * us a ratio of one byte in the CCS for each 8x16 pixels in the
> * main surface.
> */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
> { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[] = {
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions
> of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
>
[Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression
From: Dhinakaran Pandiyan
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modifier to identify
gen-12 compression. Another notable change is that decompression is
supported on all planes except cursor and on all pipes. This patch adds
decompression support for [A,X]BGR888 pixel formats.
Bspec: 18437
v2: Fix checkpatch warnings (Lucas)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +---
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ---
2 files changed, 71 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 109d4fd961c6..190adbffe055 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return cpp;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
== 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2429,6 +2436,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
@@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels
in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2480,8 +2506,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+
