Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Mon, 2016-10-17 at 11:33 +0300, Ville Syrjälä wrote: > On Fri, Oct 14, 2016 at 08:33:37PM +, Pandiyan, Dhinakaran wrote: > > On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote: > > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > > > According to BSpec, cdclk

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Mon, Oct 17, 2016 at 08:55:51AM +0200, Daniel Vetter wrote: > On Fri, Oct 14, 2016 at 07:27:39PM +, Pandiyan, Dhinakaran wrote: > > On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote: > > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > > > According to BSpec,

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Fri, Oct 14, 2016 at 08:33:37PM +, Pandiyan, Dhinakaran wrote: > On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote: > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > > enabled, port

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Fri, Oct 14, 2016 at 07:27:39PM +, Pandiyan, Dhinakaran wrote: > On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote: > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > > enabled, port

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

> -Original Message- > From: Pandiyan, Dhinakaran > Sent: Saturday, October 15, 2016 4:36 AM > To: Yang, Libin > Cc: intel-...@freedesktop.org; Nikula, Jani ; Kp, Jeeja > ; libin.y...@linux.intel.com > Subject: Re:

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Fri, 2016-10-14 at 03:09 +, Yang, Libin wrote: > Tested-by: Libin Yang > > Regards, > Libin > > Thanks Libin. Can you confirm the max. BCLK frequency we set for the audio controller? -DK > > -Original Message- > > From: Intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote: > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > > > Having a lower cdclk triggers

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Fri, 2016-10-14 at 11:40 +0300, Jani Nikula wrote: > On Thu, 13 Oct 2016, Dhinakaran Pandiyan > wrote: > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > > > Having a lower

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote: > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > > > Having a lower cdclk triggers

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, 2016-10-13 at 15:28 -0300, Paulo Zanoni wrote: > Em Qui, 2016-10-13 às 11:04 -0700, Dhinakaran Pandiyan escreveu: > > According to BSpec, cdclk has to be not less than 432 MHz with DP > > audio > > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > This is just for pre-production

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, 13 Oct 2016, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays >

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

Tested-by: Libin Yang Regards, Libin > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Dhinakaran Pandiyan > Sent: Friday, October 14, 2016 2:04 AM > To: intel-...@freedesktop.org > Cc: Nikula, Jani

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

Em Qui, 2016-10-13 às 11:04 -0700, Dhinakaran Pandiyan escreveu: > According to BSpec, cdclk has to be not less than 432 MHz with DP > audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) This is just for pre-production hardware, and we don't implement workarounds for pre-prod. A quick