Re: [Intel-gfx] [PATCH v10 08/23] drm/i915/dp: Compute DSC pipe config in atomic check
On Tue, Nov 27, 2018 at 03:57:23PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 20, 2018 at 10:37:21AM -0800, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v14:
> > Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
> > v13:
> > * Compute DSC bpc only when DSC is req to be enabled (Ville)
> > v12:
> > * Override bpp with dsc dpcd color depth (Manasi)
> > v11:
> > * Const crtc_state, reject DSC on DP without FEC (Ville)
> > * Dont set dsc_split to false (Ville)
> > v10:
> > * Add a helper for dp_dsc support (Ville)
> > * Set pipe_config to max bpp, link params for DSC for now (Ville)
> > * Compute bpp - use dp dsc support helper (Ville)
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > drivers/gpu/drm/i915/intel_display.h | 2 +-
> > drivers/gpu/drm/i915/intel_dp.c | 191 ---
> > 3 files changed, 171 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 132e978227fb..f2e6425d09ef 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6723,7 +6723,7 @@ static void compute_m_n(unsigned int m, unsigned int
> > n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..afb6435887df 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,7 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(u16 bpp, int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 2b090609bee2..78ec775aa90a 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1708,6 +1710,26 @@ struct link_config_limits {
> > int min_bpp, max_bpp;
> > };
> >
> > +static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> > +const struct intel_crtc_state
> > *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + /* FIXME: FEC needed for external DP until then reject DSC on DP */
> > + if (!intel_dp_is_edp(intel_dp))
> > + return false;
> > +
> > + return INTEL_GEN(dev_priv) >= 10 &&
> > + pipe_config->cpu_transcoder != TRANSCODER_A;
> > +}
> > +
> > +static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *pipe_config)
> > +{
> > + return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
> > + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
> > +}
> > +
> > static int
Re: [Intel-gfx] [PATCH v10 08/23] drm/i915/dp: Compute DSC pipe config in atomic check
On Tue, Nov 20, 2018 at 10:37:21AM -0800, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v14:
> Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
> v13:
> * Compute DSC bpc only when DSC is req to be enabled (Ville)
> v12:
> * Override bpp with dsc dpcd color depth (Manasi)
> v11:
> * Const crtc_state, reject DSC on DP without FEC (Ville)
> * Dont set dsc_split to false (Ville)
> v10:
> * Add a helper for dp_dsc support (Ville)
> * Set pipe_config to max bpp, link params for DSC for now (Ville)
> * Compute bpp - use dp dsc support helper (Ville)
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Reviewed-by: Anusha Srivatsa
> Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_display.h | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 191 ---
> 3 files changed, 171 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 132e978227fb..f2e6425d09ef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6723,7 +6723,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..afb6435887df 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,7 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2b090609bee2..78ec775aa90a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
> @@ -1708,6 +1710,26 @@ struct link_config_limits {
> int min_bpp, max_bpp;
> };
>
> +static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> + const struct intel_crtc_state
> *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + /* FIXME: FEC needed for external DP until then reject DSC on DP */
> + if (!intel_dp_is_edp(intel_dp))
> + return false;
> +
> + return INTEL_GEN(dev_priv) >= 10 &&
> + pipe_config->cpu_transcoder != TRANSCODER_A;
> +}
> +
> +static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *pipe_config)
> +{
> + return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
> + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
> +}
> +
> static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config)
> {
> @@ -1842,14 +1864,114 @@ intel_dp_compute_link_config_fast(struct intel_dp
> *intel_dp,
> return false;
> }
>
> +static int intel_dp_dsc_compute_bpp(struct
