Re: [Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers

2018-05-17 Thread Ramalingam C 



On Wednesday 09 May 2018 08:29 PM, Shankar, Uma wrote:



-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Ramalingam C
Sent: Tuesday, April 3, 2018 7:28 PM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
jani.nik...@linux.intel.com; Winkler, Tomas ;
Usyskin, Alexander 
Cc: Vivi, Rodrigo 
Subject: [Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers

Intel HDCP2.2 registers are defined with addr offsets and bit details.

v2:
  Replaced the arith calc with _PICK [Sean Paul]
v3:
  No changes.

Signed-off-by: Ramalingam C 
---
drivers/gpu/drm/i915/i915_reg.h | 32 
1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6a8c0ee7df1..f04ad3c15abd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8649,6 +8649,38 @@ enum skl_power_gate {
#define  HDCP_STATUS_CIPHER BIT(16)
#define  HDCP_STATUS_FRAME_CNT(x)   ((x >> 8) & 0xff)

+/* HDCP2.2 Registers */
+#define _PORTA_HDCP2_BASE  0x66800
+#define _PORTB_HDCP2_BASE  0x66500
+#define _PORTC_HDCP2_BASE  0x66600
+#define _PORTD_HDCP2_BASE  0x66700
+#define _PORTE_HDCP2_BASE  0x66A00
+#define _PORTF_HDCP2_BASE  0x66900
+#define _PORT_HDCP2_BASE(port, x)  _MMIO(_PICK(port, \
+ _PORTA_HDCP2_BASE, \
+ _PORTB_HDCP2_BASE, \
+ _PORTC_HDCP2_BASE, \
+ _PORTD_HDCP2_BASE, \
+ _PORTE_HDCP2_BASE, \
+ _PORTF_HDCP2_BASE) + x)
+
+#define HDCP2_AUTH_DDI(port)   _PORT_HDCP2_BASE(port,
0x98)
+#define   AUTH_LINK_AUTHENTICATED  BIT(31)
+#define   AUTH_LINK_TYPE   BIT(30)
+#define   AUTH_FORCE_CLR_INPUTCTR  BIT(19)
+#define   AUTH_CLR_KEYSBIT(18)
+
+#define HDCP2_CTR_DDI(port)_PORT_HDCP2_BASE(port, 0xB0)

Rename it to HDCP2_CTL_DDI to match with spec and avoid any ambiguity.

I will rename it as CTL.

--Ram



+#define   CTL_LINK_ENCRYPTION_REQ  BIT(31)
+
+#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port,
0xB4)
+#define   STREAM_ENCRYPTION_STATUS_A   BIT(31)
+#define   STREAM_ENCRYPTION_STATUS_B   BIT(30)
+#define   STREAM_ENCRYPTION_STATUS_C   BIT(29)
+#define   LINK_TYPE_STATUS BIT(22)
+#define   LINK_AUTH_STATUS BIT(21)
+#define   LINK_ENCRYPTION_STATUS   BIT(20)
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A   0x60400
#define _TRANS_DDI_FUNC_CTL_B   0x61400
--
2.7.4

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Re: [Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers

2018-05-09 Thread Shankar, Uma 


>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
>jani.nik...@linux.intel.com; Winkler, Tomas ;
>Usyskin, Alexander 
>Cc: Vivi, Rodrigo 
>Subject: [Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers
>
>Intel HDCP2.2 registers are defined with addr offsets and bit details.
>
>v2:
>  Replaced the arith calc with _PICK [Sean Paul]
>v3:
>  No changes.
>
>Signed-off-by: Ramalingam C 
>---
> drivers/gpu/drm/i915/i915_reg.h | 32 
> 1 file changed, 32 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index e6a8c0ee7df1..f04ad3c15abd 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8649,6 +8649,38 @@ enum skl_power_gate {
> #define  HDCP_STATUS_CIPHER   BIT(16)
> #define  HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
>
>+/* HDCP2.2 Registers */
>+#define _PORTA_HDCP2_BASE 0x66800
>+#define _PORTB_HDCP2_BASE 0x66500
>+#define _PORTC_HDCP2_BASE 0x66600
>+#define _PORTD_HDCP2_BASE 0x66700
>+#define _PORTE_HDCP2_BASE 0x66A00
>+#define _PORTF_HDCP2_BASE 0x66900
>+#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK(port, \
>+_PORTA_HDCP2_BASE, \
>+_PORTB_HDCP2_BASE, \
>+_PORTC_HDCP2_BASE, \
>+_PORTD_HDCP2_BASE, \
>+_PORTE_HDCP2_BASE, \
>+_PORTF_HDCP2_BASE) + x)
>+
>+#define HDCP2_AUTH_DDI(port)  _PORT_HDCP2_BASE(port,
>0x98)
>+#define   AUTH_LINK_AUTHENTICATED BIT(31)
>+#define   AUTH_LINK_TYPE  BIT(30)
>+#define   AUTH_FORCE_CLR_INPUTCTR BIT(19)
>+#define   AUTH_CLR_KEYS   BIT(18)
>+
>+#define HDCP2_CTR_DDI(port)   _PORT_HDCP2_BASE(port, 0xB0)

Rename it to HDCP2_CTL_DDI to match with spec and avoid any ambiguity.

>+#define   CTL_LINK_ENCRYPTION_REQ BIT(31)
>+
>+#define HDCP2_STATUS_DDI(port)_PORT_HDCP2_BASE(port,
>0xB4)
>+#define   STREAM_ENCRYPTION_STATUS_A  BIT(31)
>+#define   STREAM_ENCRYPTION_STATUS_B  BIT(30)
>+#define   STREAM_ENCRYPTION_STATUS_C  BIT(29)
>+#define   LINK_TYPE_STATUSBIT(22)
>+#define   LINK_AUTH_STATUSBIT(21)
>+#define   LINK_ENCRYPTION_STATUS  BIT(20)
>+
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
>--
>2.7.4
>
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