On Fri, Mar 21, 2025 at 01:35:16AM -0500, Lucas De Marchi wrote:
> On Fri, Feb 14, 2025 at 01:59:44PM -0800, Vivek Kasireddy wrote:
> > Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
> > with ECC enabled. We need to identify this scenario and add a new
> > case in xelpdp_get_dram_info() to handle it. In addition, the
> > derating value needs to be adjusted accordingly to compensate for
> > the limited bandwidth.
> >
> > Bspec: 64602
> > Cc: Matt Roper
> > Signed-off-by: Vivek Kasireddy
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 5 -
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/soc/intel_dram.c | 4
> > drivers/gpu/drm/xe/xe_device_types.h| 1 +
> > 4 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 23edc81741de..b8a9651b74d3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> > *dev_priv,
> > qi->deinterleave = 4;
> > break;
> > case INTEL_DRAM_GDDR:
> > + case INTEL_DRAM_GDDR_ECC:
> > qi->channel_width = 32;
> > break;
> > default:
> > @@ -630,9 +631,11 @@ static int xe2_hpd_get_bw_info(struct drm_i915_private
> > *i915,
> > for (i = 0; i < qi.num_points; i++) {
> > const struct intel_qgv_point *point = &qi.points[i];
> > int bw = num_channels * (qi.channel_width / 8) * point->dclk;
> > + u8 derating = i915->dram_info.type == INTEL_DRAM_GDDR_ECC ?
> > + 45 : sa->derating;
>
> looks wrong to leave the sa->derating with the wrong value and just
> patch it here.
>
> By the time intel_bw_init_hw() is called, we already have
> i915->dram_info->type.
> So maybe it'd be better to fork a struct intel_sa_info for this case and
> have the correct derating consistently? Otherwise, at least moving this
> out of the loop would be appropriate IMO.
>
> Matt, thoughts?
Yeah, I agree that creating a separate intel_sa_info structure with the
proper values for the ECC case might be the cleanest.
Matt
>
> There was a small conflict due to the move to intel_display, but
> otherwise this commit still applies.
>
> Lucas De Marchi
>
> >
> > i915->display.bw.max[0].deratedbw[i] =
> > - min(maxdebw, (100 - sa->derating) * bw / 100);
> > + min(maxdebw, (100 - derating) * bw / 100);
> > i915->display.bw.max[0].peakbw[i] = bw;
> >
> > drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index ffc346379cc2..54538b6f85df 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -305,6 +305,7 @@ struct drm_i915_private {
> > INTEL_DRAM_DDR5,
> > INTEL_DRAM_LPDDR5,
> > INTEL_DRAM_GDDR,
> > + INTEL_DRAM_GDDR_ECC,
> > } type;
> > u8 num_qgv_points;
> > u8 num_psf_gv_points;
> > diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> > b/drivers/gpu/drm/i915/soc/intel_dram.c
> > index 9e310f4099f4..f60eedb0e92c 100644
> > --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> > @@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct
> > drm_i915_private *i915)
> > drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> > dram_info->type = INTEL_DRAM_GDDR;
> > break;
> > + case 9:
> > + drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> > + dram_info->type = INTEL_DRAM_GDDR_ECC;
> > + break;
> > default:
> > MISSING_CASE(val);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 4656305dd45a..0921e957d784 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -575,6 +575,7 @@ struct xe_device {
> > INTEL_DRAM_DDR5,
> > INTEL_DRAM_LPDDR5,
> > INTEL_DRAM_GDDR,
> > + INTEL_DRAM_GDDR_ECC,
> > } type;
> > u8 num_qgv_points;
> > u8 num_psf_gv_points;
> > --
> > 2.47.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
