Re: [Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio
On 28/4/2025 5:11 pm, Loktionov, Aleksandr wrote: -Original Message- From: Intel-wired-lan On Behalf Of Faizal Rahim Sent: Monday, April 28, 2025 8:02 AM To: Nguyen, Anthony L ; Kitszel, Przemyslaw ; Andrew Lunn ; David S . Miller ; Eric Dumazet ; Jakub Kicinski ; Paolo Abeni ; Vladimir Oltean Cc: [email protected]; [email protected]; linux- [email protected]; Faizal Rahim ; Choong, Chwee Lin Subject: [Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio igc already supports enabling MAC Merge for FPE. This patch adds support for preemptible queues in taprio. Can you mention what "FPE" stands for (e.g., Frame Preemption) for better understanding? Everything else is fine for me. Reviewed-by: Aleksandr Loktionov Will update. Thanks.
Re: [Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio
> -Original Message- > From: Intel-wired-lan On Behalf Of > Faizal Rahim > Sent: Monday, April 28, 2025 8:02 AM > To: Nguyen, Anthony L ; Kitszel, Przemyslaw > ; Andrew Lunn ; > David S . Miller ; Eric Dumazet > ; Jakub Kicinski ; Paolo Abeni > ; Vladimir Oltean > Cc: [email protected]; [email protected]; linux- > [email protected]; Faizal Rahim ; > Choong, Chwee Lin > Subject: [Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue > support in taprio > > igc already supports enabling MAC Merge for FPE. This patch adds support for > preemptible queues in taprio. > Can you mention what "FPE" stands for (e.g., Frame Preemption) for better understanding? Everything else is fine for me. Reviewed-by: Aleksandr Loktionov > Changes: > 1. Introduce tx_enabled flag to control preemptible queue. tx_enabled >is set via mmsv module based on multiple factors, including link >up/down status, to determine if FPE is active or inactive. > 2. Add priority field to TXDCTL for express queue to improve data >fetch performance. > 3. Block preemptible queue setup in taprio unless reverse-tsn-txq-prio >private flag is set. Encourages adoption of standard queue priority >scheme for new features. > > Tested preemption with taprio by: > 1. Enable FPE: >ethtool --set-mm enp1s0 pmac-enabled on tx-enabled on verify-enabled on > 2. Enable private flag to reverse TX queue priority: >ethtool --set-priv-flags enp1s0 reverse-txq-prio on 3. Enable preemptible > queue in taprio: >taprio num_tc 4 map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 \ >queues 1@0 1@1 1@2 1@3 \ >fp P P P E > > Signed-off-by: Faizal Rahim > --- > drivers/net/ethernet/intel/igc/igc.h | 5 ++ > drivers/net/ethernet/intel/igc/igc_defines.h | 1 + > drivers/net/ethernet/intel/igc/igc_main.c| 12 +++- > drivers/net/ethernet/intel/igc/igc_tsn.c | 71 > drivers/net/ethernet/intel/igc/igc_tsn.h | 4 ++ > 5 files changed, 90 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/intel/igc/igc.h > b/drivers/net/ethernet/intel/igc/igc.h > index 684a11df445c..39444e61003d 100644 > --- a/drivers/net/ethernet/intel/igc/igc.h > +++ b/drivers/net/ethernet/intel/igc/igc.h > @@ -43,6 +43,7 @@ void igc_ethtool_set_ops(struct net_device *); struct > igc_fpe_t { > struct ethtool_mmsv mmsv; > u32 tx_min_frag_size; > + bool tx_enabled; > }; > > enum igc_mac_filter_type { > @@ -163,6 +164,7 @@ struct igc_ring { > bool launchtime_enable; /* true if LaunchTime is enabled */ > ktime_t last_tx_cycle; /* end of the cycle with a launchtime > transmission */ > ktime_t last_ff_cycle; /* Last cycle with an active first flag > */ > + bool preemptible; /* True if preemptible queue, false if > express queue */ > > u32 start_time; > u32 end_time; > @@ -495,6 +497,7 @@ static inline u32 igc_rss_type(const union > igc_adv_rx_desc *rx_desc) > #define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) > #define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) > #define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) > +#define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27) > > #define IGC_TXDCTL_PTHRESH(x) > FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) > #define IGC_TXDCTL_HTHRESH(x) > FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) > @@ -504,6 +507,8 @@ static inline u32 igc_rss_type(const union > igc_adv_rx_desc *rx_desc) > #define IGC_TXDCTL_QUEUE_ENABLE > FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1) > /* Transmit Software Flush */ > #define IGC_TXDCTL_SWFLUSH > FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) > +#define IGC_TXDCTL_PRIORITY(x) > FIELD_PREP(IGC_TXDCTL_PRIORITY_MASK, (x)) > +#define IGC_TXDCTL_PRIORITY_HIGH IGC_TXDCTL_PRIORITY(1) > > #define IGC_RX_DMA_ATTR \ > (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff -- > git a/drivers/net/ethernet/intel/igc/igc_defines.h > b/drivers/net/ethernet/intel/igc/igc_defines.h > index 7189dfc389ad..86b346687196 100644 > --- a/drivers/net/ethernet/intel/igc/igc_defines.h > +++ b/drivers/net/ethernet/intel/igc/igc_defines.h > @@ -588,6 +588,7 @@ > #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT0x0001 > #define IGC_TXQCTL_STRICT_CYCLE 0x0002 > #define IGC_TXQCTL_STRICT_END0x0004 > +#define IGC_TXQCTL_PREEMPTIBLE 0x0008 > #define IGC_TXQCTL_QAV_SEL_MASK 0x00C0 > #define IGC_TXQCTL_QAV_SEL_CBS0 0x0080 > #define IGC_TXQCTL_QAV_SEL_CBS1 0x00C
[Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio
igc already supports enabling MAC Merge for FPE. This patch adds
support for preemptible queues in taprio.
Changes:
1. Introduce tx_enabled flag to control preemptible queue. tx_enabled
is set via mmsv module based on multiple factors, including link
up/down status, to determine if FPE is active or inactive.
2. Add priority field to TXDCTL for express queue to improve data
fetch performance.
3. Block preemptible queue setup in taprio unless reverse-tsn-txq-prio
private flag is set. Encourages adoption of standard queue priority
scheme for new features.
Tested preemption with taprio by:
1. Enable FPE:
ethtool --set-mm enp1s0 pmac-enabled on tx-enabled on verify-enabled on
2. Enable private flag to reverse TX queue priority:
ethtool --set-priv-flags enp1s0 reverse-txq-prio on
3. Enable preemptible queue in taprio:
taprio num_tc 4 map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 1@3 \
fp P P P E
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc.h | 5 ++
drivers/net/ethernet/intel/igc/igc_defines.h | 1 +
drivers/net/ethernet/intel/igc/igc_main.c| 12 +++-
drivers/net/ethernet/intel/igc/igc_tsn.c | 71
drivers/net/ethernet/intel/igc/igc_tsn.h | 4 ++
5 files changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/intel/igc/igc.h
b/drivers/net/ethernet/intel/igc/igc.h
index 684a11df445c..39444e61003d 100644
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -43,6 +43,7 @@ void igc_ethtool_set_ops(struct net_device *);
struct igc_fpe_t {
struct ethtool_mmsv mmsv;
u32 tx_min_frag_size;
+ bool tx_enabled;
};
enum igc_mac_filter_type {
@@ -163,6 +164,7 @@ struct igc_ring {
bool launchtime_enable; /* true if LaunchTime is enabled */
ktime_t last_tx_cycle; /* end of the cycle with a launchtime
transmission */
ktime_t last_ff_cycle; /* Last cycle with an active first flag
*/
+ bool preemptible; /* True if preemptible queue, false if
express queue */
u32 start_time;
u32 end_time;
@@ -495,6 +497,7 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc
*rx_desc)
#define IGC_TXDCTL_WTHRESH_MASKGENMASK(20, 16)
#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25)
#define IGC_TXDCTL_SWFLUSH_MASKGENMASK(26, 26)
+#define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27)
#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x))
#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x))
@@ -504,6 +507,8 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc
*rx_desc)
#define IGC_TXDCTL_QUEUE_ENABLE
FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1)
/* Transmit Software Flush */
#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1)
+#define IGC_TXDCTL_PRIORITY(x) FIELD_PREP(IGC_TXDCTL_PRIORITY_MASK,
(x))
+#define IGC_TXDCTL_PRIORITY_HIGH IGC_TXDCTL_PRIORITY(1)
#define IGC_RX_DMA_ATTR \
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h
b/drivers/net/ethernet/intel/igc/igc_defines.h
index 7189dfc389ad..86b346687196 100644
--- a/drivers/net/ethernet/intel/igc/igc_defines.h
+++ b/drivers/net/ethernet/intel/igc/igc_defines.h
@@ -588,6 +588,7 @@
#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x0001
#define IGC_TXQCTL_STRICT_CYCLE0x0002
#define IGC_TXQCTL_STRICT_END 0x0004
+#define IGC_TXQCTL_PREEMPTIBLE 0x0008
#define IGC_TXQCTL_QAV_SEL_MASK0x00C0
#define IGC_TXQCTL_QAV_SEL_CBS00x0080
#define IGC_TXQCTL_QAV_SEL_CBS10x00C0
diff --git a/drivers/net/ethernet/intel/igc/igc_main.c
b/drivers/net/ethernet/intel/igc/igc_main.c
index 8562565842b1..c6e2cfd630df 100644
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -6419,6 +6419,7 @@ static int igc_qbv_clear_schedule(struct igc_adapter
*adapter)
ring->start_time = 0;
ring->end_time = NSEC_PER_SEC;
ring->max_sdu = 0;
+ ring->preemptible = false;
}
spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
@@ -6484,9 +6485,12 @@ static int igc_save_qbv_schedule(struct igc_adapter
*adapter,
if (!validate_schedule(adapter, qopt))
return -EINVAL;
- /* preemptible isn't supported yet */
- if (qopt->mqprio.preemptible_tcs)
- return -EOPNOTSUPP;
+ if (qopt->mqprio.preemptible_tcs &&
+ !(adapter->flags & IGC_FLAG_TSN_REVERSE_TXQ_PRIO)) {
+ NL_SET_ERR_MSG_MOD(qopt->extack,
+ "reverse-tsn-txq-prio private flag must be
enabled before setting preemptible tc");
+
