Re: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery
On 1/9/26 7:15 AM, Loktionov, Aleksandr wrote: -Original Message- From: Intel-wired-lan On Behalf Of Ivan Vecera Sent: Thursday, January 8, 2026 7:23 PM To: [email protected] Cc: Eric Dumazet ; Nguyen, Anthony L ; Rob Herring ; Leon Romanovsky ; Andrew Lunn ; [email protected]; Kitszel, Przemyslaw ; Kubalewski, Arkadiusz ; [email protected]; Jakub Kicinski ; Paolo Abeni ; [email protected]; Conor Dooley ; Jiri Pirko ; Richard Cochran ; Prathosh Satish ; Vadim Fedorenko ; Mark Bloch ; linux- [email protected]; Tariq Toukan ; Lobakin, Aleksander ; Jonathan Lemon ; Krzysztof Kozlowski ; Saeed Mahameed ; David S. Miller Subject: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery From: Arkadiusz Kubalewski Add DPLL support for the Intel E825-C Ethernet controller. Unlike previous generations (E810), the E825-C connects to the platform's DPLL subsystem via MUX pins defined in the system firmware (Device Tree/ACPI). Implement the following mechanisms to support this architecture: 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to locate the parent MUX pins defined in the firmware. 2. Asynchronous Registration: Since the platform DPLL driver may probe independently of the network driver, utilize the DPLL notifier chain (register_dpll_notifier). The driver listens for DPLL_PIN_CREATED events to detect when the parent MUX pins become available, then registers its own Recovered Clock (RCLK) pins as children of those parents. 3. Hardware Configuration: Implement the specific register access logic for E825-C CGU (Clock Generation Unit) registers (R10, R11). This includes configuring the bypass MUXes and clock dividers required to drive SyncE signals. 4. Split Initialization: Refactor `ice_dpll_init()` to separate the static initialization path of E810 from the dynamic, firmware- driven path required for E825-C. Co-developed-by: Ivan Vecera Signed-off-by: Ivan Vecera Co-developed-by: Grzegorz Nitka Signed-off-by: Grzegorz Nitka Signed-off-by: Arkadiusz Kubalewski --- drivers/net/ethernet/intel/ice/ice_dpll.c | 715 +-- - drivers/net/ethernet/intel/ice/ice_dpll.h | 25 + drivers/net/ethernet/intel/ice/ice_lib.c| 3 + drivers/net/ethernet/intel/ice/ice_ptp.c| 29 + drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +- drivers/net/ethernet/intel/ice/ice_tspll.c | 217 ++ drivers/net/ethernet/intel/ice/ice_tspll.h | 13 +- drivers/net/ethernet/intel/ice/ice_type.h | 6 + 8 files changed, 925 insertions(+), 92 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 4eca62688d834..06575d42de6e9 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -5,6 +5,7 @@ ... +/** + * ice_dpll_init_fwnode_pins - initialize pins from device tree + * @pf: board private structure + * @pins: pointer to pins array + * @start_idx: starting index for pins + * @count: number of pins to initialize + * + * Initialize input pins for E825 RCLK support. The parent pins (rclk0, +rclk1) + * are expected to be defined in the device tree (ACPI). This function +allocates Device Tree and ACPI are different firmware interfaces, aren't they? Writing "device tree (ACPI)" can mislead readers about where the fwnode-backed discovery is expected to come from. Will fix. The code looks good for me. Reviewed-by: Aleksandr Loktionov Thank you, Alex. Ivan
Re: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery
> -Original Message- > From: Intel-wired-lan On Behalf > Of Ivan Vecera > Sent: Thursday, January 8, 2026 7:23 PM > To: [email protected] > Cc: Eric Dumazet ; Nguyen, Anthony L > ; Rob Herring ; Leon > Romanovsky ; Andrew Lunn ; > [email protected]; Kitszel, Przemyslaw > ; Kubalewski, Arkadiusz > ; [email protected]; > Jakub Kicinski ; Paolo Abeni ; > [email protected]; Conor Dooley ; Jiri > Pirko ; Richard Cochran ; > Prathosh Satish ; Vadim Fedorenko > ; Mark Bloch ; linux- > [email protected]; Tariq Toukan ; Lobakin, > Aleksander ; Jonathan Lemon > ; Krzysztof Kozlowski ; > Saeed Mahameed ; David S. Miller > > Subject: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support > E825-C SyncE and dynamic pin discovery > > From: Arkadiusz Kubalewski > > Add DPLL support for the Intel E825-C Ethernet controller. Unlike > previous generations (E810), the E825-C connects to the platform's > DPLL subsystem via MUX pins defined in the system firmware (Device > Tree/ACPI). > > Implement the following mechanisms to support this architecture: > > 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to >locate the parent MUX pins defined in the firmware. > > 2. Asynchronous Registration: Since the platform DPLL driver may probe >independently of the network driver, utilize the DPLL notifier > chain >(register_dpll_notifier). The driver listens for DPLL_PIN_CREATED >events to detect when the parent MUX pins become available, then >registers its own Recovered Clock (RCLK) pins as children of those >parents. > > 3. Hardware Configuration: Implement the specific register access > logic >for E825-C CGU (Clock Generation Unit) registers (R10, R11). This >includes configuring the bypass MUXes and clock dividers required > to >drive SyncE signals. > > 4. Split Initialization: Refactor `ice_dpll_init()` to separate the >static initialization path of E810 from the dynamic, firmware- > driven >path required for E825-C. > > Co-developed-by: Ivan Vecera > Signed-off-by: Ivan Vecera > Co-developed-by: Grzegorz Nitka > Signed-off-by: Grzegorz Nitka > Signed-off-by: Arkadiusz Kubalewski > --- > drivers/net/ethernet/intel/ice/ice_dpll.c | 715 +-- > - > drivers/net/ethernet/intel/ice/ice_dpll.h | 25 + > drivers/net/ethernet/intel/ice/ice_lib.c| 3 + > drivers/net/ethernet/intel/ice/ice_ptp.c| 29 + > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +- > drivers/net/ethernet/intel/ice/ice_tspll.c | 217 ++ > drivers/net/ethernet/intel/ice/ice_tspll.h | 13 +- > drivers/net/ethernet/intel/ice/ice_type.h | 6 + > 8 files changed, 925 insertions(+), 92 deletions(-) > > diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c > b/drivers/net/ethernet/intel/ice/ice_dpll.c > index 4eca62688d834..06575d42de6e9 100644 > --- a/drivers/net/ethernet/intel/ice/ice_dpll.c > +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c > @@ -5,6 +5,7 @@ ... > +/** > + * ice_dpll_init_fwnode_pins - initialize pins from device tree > + * @pf: board private structure > + * @pins: pointer to pins array > + * @start_idx: starting index for pins > + * @count: number of pins to initialize > + * > + * Initialize input pins for E825 RCLK support. The parent pins > (rclk0, > +rclk1) > + * are expected to be defined in the device tree (ACPI). This > function > +allocates Device Tree and ACPI are different firmware interfaces, aren't they? Writing "device tree (ACPI)" can mislead readers about where the fwnode-backed discovery is expected to come from. The code looks good for me. Reviewed-by: Aleksandr Loktionov > + * them in the dpll subsystem and stores their indices for later > +registration > + * with the rclk pin. ... > -- > 2.52.0
[Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery
From: Arkadiusz Kubalewski
Add DPLL support for the Intel E825-C Ethernet controller. Unlike previous
generations (E810), the E825-C connects to the platform's DPLL subsystem
via MUX pins defined in the system firmware (Device Tree/ACPI).
Implement the following mechanisms to support this architecture:
1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to
locate the parent MUX pins defined in the firmware.
2. Asynchronous Registration: Since the platform DPLL driver may probe
independently of the network driver, utilize the DPLL notifier chain
(register_dpll_notifier). The driver listens for DPLL_PIN_CREATED
events to detect when the parent MUX pins become available, then
registers its own Recovered Clock (RCLK) pins as children of those
parents.
3. Hardware Configuration: Implement the specific register access logic
for E825-C CGU (Clock Generation Unit) registers (R10, R11). This
includes configuring the bypass MUXes and clock dividers required to
drive SyncE signals.
4. Split Initialization: Refactor `ice_dpll_init()` to separate the
static initialization path of E810 from the dynamic, firmware-driven
path required for E825-C.
Co-developed-by: Ivan Vecera
Signed-off-by: Ivan Vecera
Co-developed-by: Grzegorz Nitka
Signed-off-by: Grzegorz Nitka
Signed-off-by: Arkadiusz Kubalewski
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 715 +---
drivers/net/ethernet/intel/ice/ice_dpll.h | 25 +
drivers/net/ethernet/intel/ice/ice_lib.c| 3 +
drivers/net/ethernet/intel/ice/ice_ptp.c| 29 +
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +-
drivers/net/ethernet/intel/ice/ice_tspll.c | 217 ++
drivers/net/ethernet/intel/ice/ice_tspll.h | 13 +-
drivers/net/ethernet/intel/ice/ice_type.h | 6 +
8 files changed, 925 insertions(+), 92 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 4eca62688d834..06575d42de6e9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -5,6 +5,7 @@
#include "ice_lib.h"
#include "ice_trace.h"
#include
+#include
#define ICE_CGU_STATE_ACQ_ERR_THRESHOLD50
#define ICE_DPLL_PIN_IDX_INVALID 0xff
@@ -528,6 +529,92 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct
ice_dpll_pin *pin,
return ret;
}
+/**
+ * ice_dpll_pin_store_state - updates the state of pin in SW bookkeeping
+ * @pin: pointer to a pin
+ * @parent: parent pin index
+ * @state: pin state (connected or disconnected)
+ */
+static void
+ice_dpll_pin_store_state(struct ice_dpll_pin *pin, int parent, bool state)
+{
+ pin->state[parent] = state ? DPLL_PIN_STATE_CONNECTED :
+ DPLL_PIN_STATE_DISCONNECTED;
+}
+
+/**
+ * ice_dpll_rclk_update_e825c - updates the state of rclk pin on e825c device
+ * @pf: private board struct
+ * @pin: pointer to a pin
+ *
+ * Update struct holding pin states info, states are separate for each parent
+ *
+ * Context: Called under pf->dplls.lock
+ * Return:
+ * * 0 - OK
+ * * negative - error
+ */
+static int ice_dpll_rclk_update_e825c(struct ice_pf *pf,
+ struct ice_dpll_pin *pin)
+{
+ u8 rclk_bits;
+ int err;
+ u32 reg;
+
+ if (pf->dplls.rclk.num_parents > ICE_SYNCE_CLK_NUM)
+ return -EINVAL;
+
+ err = ice_read_cgu_reg(&pf->hw, ICE_CGU_R10, ®);
+ if (err)
+ return err;
+
+ rclk_bits = FIELD_GET(ICE_CGU_R10_SYNCE_S_REF_CLK, reg);
+ ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK0, rclk_bits ==
+ (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C));
+
+ err = ice_read_cgu_reg(&pf->hw, ICE_CGU_R11, ®);
+ if (err)
+ return err;
+
+ rclk_bits = FIELD_GET(ICE_CGU_R11_SYNCE_S_BYP_CLK, reg);
+ ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK1, rclk_bits ==
+ (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C));
+
+ return 0;
+}
+
+/**
+ * ice_dpll_rclk_update - updates the state of rclk pin on a device
+ * @pf: private board struct
+ * @pin: pointer to a pin
+ * @port_num: port number
+ *
+ * Update struct holding pin states info, states are separate for each parent
+ *
+ * Context: Called under pf->dplls.lock
+ * Return:
+ * * 0 - OK
+ * * negative - error
+ */
+static int ice_dpll_rclk_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
+ u8 port_num)
+{
+ int ret;
+
+ for (u8 parent = 0; parent < pf->dplls.rclk.num_parents; parent++) {
+ ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &parent, &port_num,
+&pin->flags[parent], NULL);
+ if (ret)
+ return ret;
+
+ ice_dpll_pin_store_state(pin, parent,
+ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN
