[v9, 5/7] powerpc/fsl: move mpc85xx.h to include/linux/fsl

Move mpc85xx.h to include/linux/fsl and rename it to svr.h as a common header file. It has been used for mpc85xx and it will be used for ARM-based SoC as well. Signed-off-by: Yangbo Lu Acked-by: Wolfram Sang Acked-by: Stephen Boyd

[v9, 4/7] dt: move guts devicetree doc out of powerpc directory

Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/ since it's used by not only PowerPC but also ARM. And add a specification for 'little-endian' property. Signed-off-by: Yangbo Lu Acked-by: Scott Wood Acked-by: Rob Herring

[v9, 3/7] soc: fsl: add GUTS driver for QorIQ platforms

The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds GUTS driver to manage and access global utilities block. Signed-off-by: Yangbo Lu

[v9, 1/7] Documentation: DT: update Freescale DCFG compatible

Update Freescale DCFG compatible with 'fsl,-dcfg' instead of 'fsl,ls1021a-dcfg' to include more chips such as ls1021a, ls1043a, and ls2080a. Signed-off-by: Yangbo Lu --- Changes for v8: - Added this patch Changes for v9: - Added a list for the possible

[v9, 0/7] Fix eSDHC host version register bug

This patchset is used to fix a host version register bug in the T4240-R1.0-R2.0 eSDHC controller. To get the SoC version and revision, it's needed to add the GUTS driver to access the global utilities registers. So, the first four patches are to add the GUTS driver. The following patches except

[v9, 2/7] ARM64: dts: ls2080a: add device configuration node

Add the dts node for device configuration unit that provides general purpose configuration and status for the device. Signed-off-by: Yangbo Lu Acked-by: Scott Wood --- Changes for v5: - Added this patch Changes for v6: - None Changes for v7:

Re: [RFC PATCH v1 15/18] x86: Enable memory encryption on the APs

On 05/01/2016 05:10 PM, Huang, Kai wrote: > > > On 4/27/2016 10:58 AM, Tom Lendacky wrote: >> Add support to set the memory encryption enable flag on the APs during >> realmode initialization. When an AP is started it checks this flag, and >> if set, enables memory encryption on its core. >> >>

Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR

Hi Robin, On Tue, May 03, 2016 at 12:15:52PM +0100, Robin Murphy wrote: >On 03/05/16 11:15, Peng Fan wrote: >>According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, >>You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. >> >>So before clearing ARM_MMU500_ACTLR_CPRE of each

Re: [PATCH v8 6/8] iommu/msi-iommu: iommu_msi_domain

Hi Alex, On 05/02/2016 10:23 PM, Alex Williamson wrote: > Hi Eric, > > On Mon, 2 May 2016 17:48:13 +0200 > Eric Auger wrote: > >> Hi Alex, >> On 04/29/2016 12:27 AM, Alex Williamson wrote: >>> On Thu, 28 Apr 2016 08:15:21 + >>> Eric Auger

Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR

On 03/05/16 11:15, Peng Fan wrote: According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. So before clearing ARM_MMU500_ACTLR_CPRE of each context bank, need clear CACHE_LOCK bit of ACR register first. Ah, good catch - I

RE: [PATCH 5/5] vfio-pci: Allow to mmap MSI-X table if interrupt remapping is supported

> From: Yongji Xie > Sent: Wednesday, April 27, 2016 8:43 PM > > This patch enables mmapping MSI-X tables if hardware supports > interrupt remapping which can ensure that a given pci device > can only shoot the MSIs assigned for it. > > With MSI-X table mmapped, we also need to expose the >

RE: [PATCH 5/5] vfio-pci: Allow to mmap MSI-X table if interrupt remapping is supported

> From: Yongji Xie [mailto:xyj...@linux.vnet.ibm.com] > Sent: Tuesday, May 03, 2016 2:08 PM > > On 2016/5/3 13:34, Tian, Kevin wrote: > > >> From: Yongji Xie > >> Sent: Wednesday, April 27, 2016 8:43 PM > >> > >> This patch enables mmapping MSI-X tables if hardware supports > >> interrupt

[PATCH] iommu/arm-smmu: clear cache lock bit of ACR

According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. So before clearing ARM_MMU500_ACTLR_CPRE of each context bank, need clear CACHE_LOCK bit of ACR register first. Signed-off-by: Peng Fan Cc: Will

Re: [PATCH 5/5] vfio-pci: Allow to mmap MSI-X table if interrupt remapping is supported

On 2016/5/3 14:22, Tian, Kevin wrote: From: Yongji Xie [mailto:xyj...@linux.vnet.ibm.com] Sent: Tuesday, May 03, 2016 2:08 PM On 2016/5/3 13:34, Tian, Kevin wrote: From: Yongji Xie Sent: Wednesday, April 27, 2016 8:43 PM This patch enables mmapping MSI-X tables if hardware supports

Re: [PATCH 5/5] vfio-pci: Allow to mmap MSI-X table if interrupt remapping is supported

On 2016/5/3 13:34, Tian, Kevin wrote: From: Yongji Xie Sent: Wednesday, April 27, 2016 8:43 PM This patch enables mmapping MSI-X tables if hardware supports interrupt remapping which can ensure that a given pci device can only shoot the MSIs assigned for it. With MSI-X table mmapped, we also