RE: [PATCH V3 2/7] documentation: iommu: Add bindings for msm, iommu-v0 ip

Hi, > > The MSM IOMMU is an implementation compatible with the ARM VMSA > short > > descriptor page tables. It provides address translation for bus > > masters outside of the CPU, each connected to the IOMMU through a port > called micro-TLB. > > Adding the DT bindings for the same. > > > >

[v10, 5/7] powerpc/fsl: move mpc85xx.h to include/linux/fsl

Move mpc85xx.h to include/linux/fsl and rename it to svr.h as a common header file. It has been used for mpc85xx and it will be used for ARM-based SoC as well. Signed-off-by: Yangbo Lu Acked-by: Wolfram Sang Acked-by: Stephen Boyd

[v10, 4/7] dt: move guts devicetree doc out of powerpc directory

Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/ since it's used by not only PowerPC but also ARM. And add a specification for 'little-endian' property. Signed-off-by: Yangbo Lu Acked-by: Scott Wood Acked-by: Rob Herring

[v10, 6/7] MAINTAINERS: add entry for Freescale SoC drivers

Add maintainer entry for Freescale SoC drivers including the QE library and the GUTS driver now. Also add maintainer for QE library. Signed-off-by: Yangbo Lu Acked-by: Scott Wood Acked-by: Qiang Zhao --- Changes for v8: - Added

[v10, 3/7] soc: fsl: add GUTS driver for QorIQ platforms

The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds GUTS driver to manage and access global utilities block. Signed-off-by: Yangbo Lu

[v10, 7/7] mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0

The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version. Acturally the right version numbers should be VVN=0x13 and SVN = 0x1. This patch adds the GUTS driver support for eSDHC driver to get SVR(System version register). And fix host version to avoid that incorrect version

[v10, 2/7] ARM64: dts: ls2080a: add device configuration node

Add the dts node for device configuration unit that provides general purpose configuration and status for the device. Signed-off-by: Yangbo Lu Acked-by: Scott Wood --- Changes for v5: - Added this patch Changes for v6: - None Changes for v7:

[v10, 1/7] Documentation: DT: update Freescale DCFG compatible

Update Freescale DCFG compatible with 'fsl,-dcfg' instead of 'fsl,ls1021a-dcfg' to include more chips such as ls1021a, ls1043a, and ls2080a. Signed-off-by: Yangbo Lu --- Changes for v8: - Added this patch Changes for v9: - Added a list for the possible

[v10, 0/7] Fix eSDHC host version register bug

This patchset is used to fix a host version register bug in the T4240-R1.0-R2.0 eSDHC controller. To get the SoC version and revision, it's needed to add the GUTS driver to access the global utilities registers. So, the first four patches are to add the GUTS driver. The following patches except

RE: [v9, 6/7] MAINTAINERS: add entry for Freescale SoC driver

Thanks a lot, Scott and Qiang. Will change 'DRIVER' to 'DRIVERS' and update the patchset with your acts. Best regards, Yangbo Lu > -Original Message- > From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc- > ow...@vger.kernel.org] On Behalf Of Scott Wood > Sent: Thursday, May 05,

RE: [v9, 6/7] MAINTAINERS: add entry for Freescale SoC driver

On Wed, 2016-05-04 at 11:24 +0800, Yangbo Lu wrote: > -Original Message- > From: Yangbo Lu [mailto:yangbo...@nxp.com] > Sent: Wednesday, May 04, 2016 11:25 AM > To: linux-...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;

Re: [PATCH v8 7/8] genirq/msi: map/unmap the MSI doorbells on msi_domain_alloc/free_irqs

Hi Marc, On 05/04/2016 03:21 PM, Marc Zyngier wrote: > On 28/04/16 09:22, Eric Auger wrote: >> This patch handles the iommu mapping of MSI doorbells that require to >> be mapped in an iommu domain. This happens on msi_domain_alloc/free_irqs >> since this is called in code that can sleep

[PATCH v9 0/8] KVM PCIe/MSI passthrough on ARM/ARM64: kernel part 2/3: msi changes

This series implements the MSI address mapping/unmapping in the MSI layer. IOMMU binding happens on pci_enable_msi since this function can sleep and return errors. On msi_domain_set_affinity, msi_domain_(de)activate, which are not allowed to sleep, we simply look for the already existing binding.

[PATCH v9 4/8] genirq/msi: msi_compose wrapper

Currently the MSI message is composed by directly calling irq_chip_compose_msi_msg and erased by setting the memory to zero. On some platforms, we will need to complexify this composition to properly handle MSI emission through IOMMU. Also we will need to track when the MSI message is erased. We

[PATCH v9 8/8] genirq/msi: use the MSI doorbell's IOVA when requested

On MSI message composition we now use the MSI doorbell's IOVA in place of the doorbell's PA in case the device is upstream to an IOMMU that requires MSI addresses to be mapped. The doorbell's allocation and mapping happened on an early stage (pci_enable_msi). Signed-off-by: Eric Auger

[PATCH v9 7/8] genirq/msi: map/unmap the MSI doorbells on msi_domain_alloc/free_irqs

This patch handles the iommu mapping of MSI doorbells that require to be mapped in an iommu domain. This happens on msi_domain_alloc/free_irqs since this is called in code that can sleep (pci_enable/disable_msi): iommu_map/unmap is not stated as atomic. On msi_domain_(de)activate and

[PATCH v9 1/8] genirq/msi: Add a new MSI_FLAG_IRQ_REMAPPING flag

Let's introduce a new msi_domain_info flag value, MSI_FLAG_IRQ_REMAPPING meant to tell the domain supports IRQ REMAPPING, also known as Interrupt Translation Service. On Intel HW this IRQ remapping capability is abstracted on IOMMU side while on ARM it is abstracted on MSI controller side. This

[PATCH v9 3/8] genirq/msi: export msi_get_domain_info

We plan to use msi_get_domain_info in VFIO module so let's export it. Signed-off-by: Eric Auger --- v2 -> v3: - remove static implementation in case CONFIG_PCI_MSI_IRQ_DOMAIN is not set --- kernel/irq/msi.c | 1 + 1 file changed, 1 insertion(+) diff --git

[GIT PULL] iommu/arm-smmu: Updates for 4.7

Hi Joerg, Please pull the following arm-smmu updates for 4.7. The highlights are: * Support for 64k pages with SMMUv1 implementations (e.g MMU-401) * Remove open-coded 64-bit MMIO accessors * Initial support for 16-bit VMIDs, as supported by some ThunderX SMMU implementations * A

Re: [PATCH v8 7/8] genirq/msi: map/unmap the MSI doorbells on msi_domain_alloc/free_irqs

On 28/04/16 09:22, Eric Auger wrote: > This patch handles the iommu mapping of MSI doorbells that require to > be mapped in an iommu domain. This happens on msi_domain_alloc/free_irqs > since this is called in code that can sleep (pci_enable/disable_msi): > iommu_map/unmap is not stated as atomic.

Re: [PATCH v9 7/7] vfio/type1: return MSI geometry through VFIO_IOMMU_GET_INFO capability chains

Hi Alex, On 05/04/2016 01:54 PM, Eric Auger wrote: > This patch allows the user-space to retrieve the MSI geometry. The > implementation is based on capability chains, now also added to > VFIO_IOMMU_GET_INFO. If you prefer we could consider this patch outside of the main series since it brings

[PATCH v9 7/7] vfio/type1: return MSI geometry through VFIO_IOMMU_GET_INFO capability chains

This patch allows the user-space to retrieve the MSI geometry. The implementation is based on capability chains, now also added to VFIO_IOMMU_GET_INFO. The returned info comprise: - whether the MSI IOVA are constrained to a reserved range (x86 case) and in the positive, the start/end of the

[PATCH v9 1/7] vfio: introduce a vfio_dma type field

We introduce a vfio_dma type since we will need to discriminate different types of dma slots: - VFIO_IOVA_USER: IOVA region used to map user vaddr - VFIO_IOVA_RESERVED: IOVA region reserved to map host device PA such as MSI doorbells Signed-off-by: Eric Auger --- v6 ->

[PATCH v9 0/7] KVM PCIe/MSI passthrough on ARM/ARM64: kernel part 3/3: vfio changes

This series allows the user-space to register a reserved IOVA domain. This completes the kernel integration of the whole functionality on top of part 1 (v9) & 2 (v8). It also depends on [PATCH 1/3] iommu: Add MMIO mapping type series, http://comments.gmane.org/gmane.linux.kernel.iommu/12869 We

[PATCH v9 3/7] vfio/type1: bypass unmap/unpin and replay for VFIO_IOVA_RESERVED slots

Before allowing the end-user to create VFIO_IOVA_RESERVED dma slots, let's implement the expected behavior for removal and replay. As opposed to user dma slots, IOVAs are not systematically bound to PAs and PAs are not pinned. VFIO just initializes the IOVA "aperture". IOVAs are allocated outside

[PATCH v9 6/7] iommu/arm-smmu: do not advertise IOMMU_CAP_INTR_REMAP

Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu(-v3). Indeed the irq_remapping capability is abstracted on irqchip side for ARM as opposed to Intel IOMMU featuring IRQ remapping HW. So to check IRQ remapping capability, the msi domain needs to be checked instead. This commit needs to be

[PATCH v9 2/7] vfio/type1: vfio_find_dma accepting a type argument

In our RB-tree we now have slots of different types (USER and RESERVED). It becomes useful to be able to search for dma slots of a specific type or any type. This patch proposes an implementation for that modality and also changes the existing callers using the USER type. Signed-off-by: Eric

[PATCH v9 4/7] vfio: allow reserved msi iova registration

The user is allowed to register a reserved MSI IOVA range by using the DMA MAP API and setting the new flag: VFIO_DMA_MAP_FLAG_MSI_RESERVED_IOVA. This region is stored in the vfio_dma rb tree. At that point the iova range is not mapped to any target address yet. The host kernel will use those iova

[PATCH v9 5/7] vfio/type1: also check IRQ remapping capability at msi domain

On x86 IRQ remapping is abstracted by the IOMMU. On ARM this is abstracted by the msi controller. vfio_safe_irq_domain allows to check whether interrupts are "safe" for a given device. They are if the device does not use MSI or if the device uses MSI and the msi-parent controller supports IRQ

[PATCH v9 1/8] iommu: Add iommu_domain_msi_geometry and DOMAIN_ATTR_MSI_GEOMETRY

Introduce a new DOMAIN_ATTR_MSI_GEOMETRY domain attribute. It enables to query the aperture of the IOVA window dedicated to MSIs and test whether the MSIs must be mapped with the IOMMU-MSI API. x86 IOMMUs will typically expose an MSI aperture matching the 1MB region [FEE0_h - FEF0_000h]

[PATCH v9 3/8] iommu: introduce an msi cookie

This opaque pointer will enable to store information about msi iommu mappings. Signed-off-by: Eric Auger --- v7 -> v8: remove spinlock and RB tree v5 -> v6: - initialize reserved_binding_list - use a spinlock instead of a mutex --- include/linux/iommu.h | 1 + 1 file

[PATCH v9 8/8] iommu/arm-smmu: get/put the msi cookie

For IOMMU_DOMAIN_UNMANAGED type we now also get the msi cookie in both arm-smmu and arm-smmu-v3. This initializes resources for MSI doorbell mapping. Signed-off-by: Eric Auger --- drivers/iommu/arm-smmu-v3.c | 16 drivers/iommu/arm-smmu.c| 15

[PATCH v9 2/8] iommu/arm-smmu: initialize the msi geometry and advertise iommu-msi support

On ARM, MSI write transactions from device upstream to the smmu are conveyed through the iommu. Therefore target physical addresses must be mapped and DOMAIN_ATTR_MSI_GEOMETRY advertises the support of the IOMMU-MSI API. Signed-off-by: Eric Auger --- v8 -> v9: - reword

[PATCH v9 4/8] iommu/msi-iommu: initialization

iommu_get/put_msi_cookie allocates/frees the resource used to store and ref count the MSI doorbell mappings. iommu_msi_set_aperture initializes the iova domain used for MSI IOVA allocation and sets the iommu domain's msi geometry. The implementation relies on dma-iommu API and iova API. New msi

[PATCH v9 6/8] iommu/msi-iommu: iommu_msi_domain

This function checks whether - the device belongs to a non default iommu domain - this iommu domain requires the MSI address to be mapped. If those conditions are met, the function returns the iommu domain to be used for mapping the MSI doorbell; else it returns NULL. Signed-off-by: Eric Auger

[PATCH v9 0/8] KVM PCIe/MSI passthrough on ARM/ARM64: kernel part 1/3: iommu changes

This series introduces the msi-iommu api used to: - allocate/free resources for MSI IOMMU mapping - set the MSI iova window aperture - map/unmap physical addresses onto MSI IOVAs. - determine whether an msi needs to be iommu mapped - overwrite an msi_msg PA address with its pre-allocated/mapped

[PATCH v9 7/8] iommu/msi-iommu: iommu_msi_msg_pa_to_va

Introduce iommu_msi_msg_pa_to_va whose role consists in detecting whether the device's MSIs must to be mapped into an IOMMU. It case it must, the function overrides the MSI msg originally composed and replaces the doorbell's PA by a pre-allocated and pre-mapped reserved IOVA. In case the

Re: [v9, 6/7] MAINTAINERS: add entry for Freescale SoC driver

On 4 May 2016 at 05:24, Yangbo Lu wrote: > Add maintainer entry for Freescale SoC driver including > the QE library and the GUTS driver now. Also add maintainer > for QE library. > > Signed-off-by: Yangbo Lu So I need an ack from Scott and Qiang for this