Re: dma-coherent: fix dma_declare_coherent_memory() logic error

On 9/5/2017 4:10 AM, Arnd Bergmann wrote: > A recent change interprets the return code of dma_init_coherent_memory > as an error value, but it is instead a boolean, where 'true' indicates > success. This leads causes the caller to always do the wrong thing, > and also triggers a compile-time

[RFC] iommu: arm-smmu: stall support

Adds a new domain property for iommu clients to opt-in to stalling with asynchronous resume, and for the client to determine if the iommu supports this. Current motivation is that: a) On 8x96/a530, if we don't enable CFCFG (or HUPCF) then non- faulting translations which are happening

[PATCH v7 4/5] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers

IOMMU drivers can use this to implement their .get_resv_regions callback for HW MSI specific reservations(e.g. ARM GICv3 ITS MSI region). Signed-off-by: Shameer Kolothum [John: added DT support] Signed-off-by: John Garry ---

[PATCH v7 0/5] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)

On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI

[PATCH v7 2/5] ACPI/IORT: Add msi address regions reservation helper

On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the

[PATCH v7 3/5] iommu/of: Add msi address regions reservation helper

From: John Garry On some platforms msi-controller address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper

[PATCH v7 5/5] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the

[PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801

From: John Garry The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMU mappings for MSI transactions. On these platforms, GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64