A quick update on invalidations before I leave for holidays, since we're
struggling to define useful semantics. I worked on the virtio-iommu
prototype for vSVA, so I tried to pin down what I think is needed for vSVA
invalidation in the host. I don't know whether the VT-d and AMD emulations
can
Hi Lorenzo/Robin/Will,
Since this has all the necessary reviewed-by from all concerned now(Thanks to
all),
just wondering how this will be picked up? through iort or iommu?
Please let me know.
Thanks,
Shameer
> -Original Message-
> From: Shameerali Kolothum Thodi
> Sent: Thursday,
On Thu, 14 Dec 2017 16:09:55 +,
Shameer Kolothum wrote:
>
> On some platforms msi parent address regions have to be excluded from
> normal IOVA allocation in that they are detected and decoded in a HW
> specific way by system components and so they cannot be considered normal
> IOVA address
On Thu, Dec 14, 2017 at 04:09:55PM +, Shameer Kolothum wrote:
> On some platforms msi parent address regions have to be excluded from
> normal IOVA allocation in that they are detected and decoded in a HW
> specific way by system components and so they cannot be considered normal
> IOVA
