Re: [PATCH v7 1/6] base: power: runtime: Export pm_runtime_get/put_suppliers

Hi Vivek, On Wed, Feb 7, 2018 at 7:31 PM, Vivek Gautam wrote: > The device link allows the pm framework to tie the supplier and > consumer. So, whenever the consumer is powered-on the supplier > is powered-on first. > > There are however cases in which the consumer

RE: [PATCH 02/37] iommu/sva: Bind process address spaces to devices

> From: Jean-Philippe Brucker > Sent: Tuesday, February 13, 2018 2:33 AM > > Add bind() and unbind() operations to the IOMMU API. Device drivers can > use them to share process page tables with their devices. bind_group() > is provided for VFIO's convenience, as it needs to provide a coherent >

RE: [PATCH 01/37] iommu: Introduce Shared Virtual Addressing API

> From: Jean-Philippe Brucker > Sent: Tuesday, February 13, 2018 2:33 AM > > Shared Virtual Addressing (SVA) provides a way for device drivers to bind > process address spaces to devices. This requires the IOMMU to support the > same page table format as CPUs, and requires the system to support

dma mapping fixes for 4.16

Below are a few small fixups for the dma mapping changes in 4.16-rc1. The most urgent one is the ia64 compile fix. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu

[PATCH 4/4] dma-mapping: fix a comment typo

Reported-by: Randy Dunlap Signed-off-by: Christoph Hellwig --- include/linux/dma-mapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 34fe8463d10e..eb9eab4ecd6d 100644

[PATCH 1/4] ia64: fix build failure with CONFIG_SWIOTLB

From: Corentin Labbe arch/ia64/kernel/pci-swiotlb.c is removed in commit 4fac8076df85 ("ia64: clean up swiotlb support") but pci-swiotlb.o is still present in Makefile, and so build fail when CONFIG_SWIOTLB is enabled. Fix the build failure by removing pci-swiotlb.o from

[PATCH 3/4] dma-direct: comment the dma_direct_free calling convention

Signed-off-by: Christoph Hellwig --- lib/dma-direct.c | 4 1 file changed, 4 insertions(+) diff --git a/lib/dma-direct.c b/lib/dma-direct.c index fdc733cf9e30..c9e8e21cb334 100644 --- a/lib/dma-direct.c +++ b/lib/dma-direct.c @@ -84,6 +84,10 @@ void *dma_direct_alloc(struct

[PATCH 2/4] dma-direct: mark as is_phys

Various PCI_DMA_BUS_IS_PHYS implementations rely on this flag to make proper decisions for block and networking addressability. Signed-off-by: Christoph Hellwig --- lib/dma-direct.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/dma-direct.c b/lib/dma-direct.c index

Re: [PATCH 29/37] iommu/arm-smmu-v3: Add stall support for platform devices

Hi, On 2018/2/13 2:33, Jean-Philippe Brucker wrote: The SMMU provides a Stall model for handling page faults in platform devices. It is similar to PCI PRI, but doesn't require devices to have their own translation cache. Instead, faulting transactions are parked and the OS is given a chance to

Re: pata-macio WARNING at dmam_alloc_coherent+0xec/0x110

On Mon, Feb 12, 2018 at 10:52:46PM +0200, Meelis Roos wrote: > I tested 4.16-rc1 on my PowerMac G4 and got the following warning from > macio pata driver. Since pata-macio has no recent changes, dma-mapping.h > changes seem to be related. Thje are, as they add just that warning. But the root

Re: [PATCH] headers: untangle kmemleak.h from mm.h

On 02/12/2018 04:28 AM, Michael Ellerman wrote: > Randy Dunlap writes: > >> From: Randy Dunlap >> >> Currently #includes for no obvious >> reason. It looks like it's only a convenience, so remove kmemleak.h >> from slab.h and add to any users of

pata-macio WARNING at dmam_alloc_coherent+0xec/0x110

I tested 4.16-rc1 on my PowerMac G4 and got the following warning from macio pata driver. Since pata-macio has no recent changes, dma-mapping.h changes seem to be related. [0.228408] MacIO PCI driver attached to Keylargo chipset [1.283931] pata-macio 0.0001f000:ata-4: Activating

Re: [PATCH] headers: untangle kmemleak.h from mm.h

On 02/12/2018 04:28 AM, Michael Ellerman wrote: > Randy Dunlap writes: > >> From: Randy Dunlap >> >> Currently #includes for no obvious >> reason. It looks like it's only a convenience, so remove kmemleak.h >> from slab.h and add to any users of

[PATCH 36/37] iommu/arm-smmu-v3: Add support for PCI PASID

Enable PASID for PCI devices that support it. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 54 + 1 file changed, 54 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c

[PATCH 37/37] vfio: Add support for Shared Virtual Addressing

Add two new ioctl for VFIO containers. VFIO_IOMMU_BIND_PROCESS creates a bond between a container and a process address space, identified by a device-specific ID named PASID. This allows the device to target DMA transactions at the process virtual addresses without a need for mapping and unmapping

[PATCH 34/37] PCI: Make "PRG Response PASID Required" handling common

The PASID ECN to the PCIe spec added a bit in the PRI status register that allows a Function to declare whether a PRG Response should contain the PASID prefix or not. Move the helper that accesses it from amd_iommu into the PCI subsystem, renaming it to be consistent with the current PCI Express

[PATCH 35/37] iommu/arm-smmu-v3: Add support for PRI

For PCI devices that support it, enable the PRI capability and handle PRI Page Requests with the generic fault handler. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 174 ++-- 1 file changed, 119

[PATCH 33/37] iommu/arm-smmu-v3: Disable tagged pointers

The ARM architecture has a "Top Byte Ignore" (TBI) option that makes the MMU mask out bits [63:56] of an address, allowing a userspace application to store data in its pointers. This option is incompatible with PCI ATS. If TBI is enabled in the SMMU and userspace triggers DMA transactions on

[PATCH 32/37] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops

The core calls us when an mm is modified. Perform the required ATC invalidations. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c

[PATCH 31/37] iommu/arm-smmu-v3: Add support for PCI ATS

PCIe devices can implement their own TLB, named Address Translation Cache (ATC). Enable Address Translation Service (ATS) for devices that support it and send them invalidation requests whenever we invalidate the IOTLBs. Range calculation - The invalidation packet itself is a

[PATCH 30/37] ACPI/IORT: Check ATS capability in root complex nodes

Root complex node in IORT has a bit telling whether it supports ATS or not. Store this bit in the IOMMU fwspec when setting up a device, so it can be accessed later by an IOMMU driver. Use the negative version (NO_ATS) at the moment because it's not clear if/how the bit needs to be integrated in

[PATCH 26/37] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update

If the SMMU supports it and the kernel was built with HTTU support, enable hardware update of access and dirty flags. This is essential for shared page tables, to reduce the number of access faults on the fault queue. We can still enable HTTU if CPUs don't support it, because the kernel always

[PATCH 29/37] iommu/arm-smmu-v3: Add stall support for platform devices

The SMMU provides a Stall model for handling page faults in platform devices. It is similar to PCI PRI, but doesn't require devices to have their own translation cache. Instead, faulting transactions are parked and the OS is given a chance to fix the page tables and retry the transaction. Enable

[PATCH 22/37] iommu/arm-smmu-v3: Add support for VHE

ARMv8.1 extensions added Virtualization Host Extensions (VHE), which allow to run a host kernel at EL2. When using normal DMA, Device and CPU address spaces are dissociated, and do not need to implement the same capabilities, so VHE hasn't been used in the SMMU until now. With shared address

[PATCH 23/37] iommu/arm-smmu-v3: Enable broadcast TLB maintenance

The SMMUv3 can handle invalidation targeted at TLB entries with shared ASIDs. If the implementation supports broadcast TLB maintenance, enable it and keep track of it in a feature bit. The SMMU will then be affected by inner-shareable TLB invalidations from other agents. A major side-effect of

[PATCH 28/37] iommu/arm-smmu-v3: Maintain a SID->device structure

When handling faults from the event or PRI queue, we need to find the struct device associated to a SID. Add a rb_tree to keep track of SIDs. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 105 1

[PATCH 27/37] iommu/arm-smmu-v3: Register fault workqueue

When using PRI or Stall, the PRI or event handler enqueues faults into the core fault queue. Register it based on the SMMU features. When the core stops using a PASID, it notifies the SMMU to flush all instances of this PASID from the PRI queue. Add a way to flush the PRI and event queue. PRI and

[PATCH 25/37] iommu/arm-smmu-v3: Implement mm operations

Hook mm operations to support PASID and page table sharing with the SMMUv3: * mm_alloc allocates a context descriptor. * mm_free releases the context descriptor. * mm_attach checks device capabilities and writes the context descriptor. * mm_detach clears the context descriptor and sends required

[PATCH 24/37] iommu/arm-smmu-v3: Add SVA feature checking

Aggregate all sanity-checks for sharing CPU page tables with the SMMU under a single ARM_SMMU_FEAT_SVA bit. For PCIe SVA, users also need to check FEAT_ATS and FEAT_PRI. For platform SVM, they will most likely have to check FEAT_STALLS. Signed-off-by: Jean-Philippe Brucker

[PATCH 21/37] iommu/arm-smmu-v3: Seize private ASID

The SMMU has a single ASID space, the union of shared and private ASID sets. This means that the PASID lib competes with the arch allocator for ASIDs. Shared ASIDs are those of Linux processes, allocated by the arch, and contribute in broadcast TLB maintenance. Private ASIDs are allocated by the

[PATCH 13/37] arm64: mm: Pin down ASIDs for sharing mm with devices

To enable address space sharing with the IOMMU, introduce mm_context_get() and mm_context_put(), that pin down a context and ensure that it will keep its ASID after a rollover. Pinning is necessary because a device constantly needs a valid ASID, unlike tasks that only require one when running.

[PATCH 12/37] iommu/of: Add stall and pasid properties to iommu_fwspec

Add stall and pasid properties to iommu_fwspec, and fill them when dma-can-stall and pasid-bits properties are present in the device tree. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/of_iommu.c | 12 include/linux/iommu.h| 2 ++ 2

[PATCH 19/37] iommu/arm-smmu-v3: Add second level of context descriptor table

The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices that support more than 1024 SSIDs now have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated on demand. Signed-off-by: Jean-Philippe Brucker

[PATCH 15/37] iommu/io-pgtable-arm: Factor out ARM LPAE register defines

For SVA, we'll need to extract CPU page table information and mirror it in the substream setup. Move relevant defines to a common header. Fix TCR_SZ_MASK while we're at it. Signed-off-by: Jean-Philippe Brucker --- MAINTAINERS| 1 +

[PATCH 16/37] iommu: Add generic PASID table library

Add a small API within the IOMMU subsystem to handle different formats of PASID tables. It uses the same principle as io-pgtable: * The IOMMU driver registers a PASID table with some invalidation callbacks. * The pasid-table lib allocates a set of tables of the right format, and returns an

[PATCH 18/37] iommu/arm-smmu-v3: Add support for Substream IDs

At the moment, the SMMUv3 driver offers only one stage-1 or stage-2 address space to each device. SMMUv3 allows to associate multiple address spaces per device. In addition to the Stream ID (SID), that identifies a device, we can now have Substream IDs (SSID) identifying an address space. In PCIe

[PATCH 20/37] iommu/arm-smmu-v3: Share process page tables

With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR, MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split into two sets, shared and private. Shared ASIDs correspond to those obtained from the arch ASID allocator, and private ASIDs are used for "classic"

[PATCH 17/37] iommu/arm-smmu-v3: Move context descriptor code

In order to add support for substream ID, move the context descriptor code into a separate library. At the moment it only manages context descriptor 0, which is used for non-PASID translations. One important behavior change is the ASID allocator, which is now global instead of per-SMMU. If we end

[PATCH 14/37] iommu/arm-smmu-v3: Link domains and devices

When removing a mapping from a domain, we need to send an invalidation to all devices that might have stored it in their Address Translation Cache (ATC). In addition when updating the context descriptor of a live domain, we'll need to send invalidations for all devices attached to it. Maintain a

[PATCH 09/37] iommu/fault: Let handler return a fault response

It is really convenient to let fault handlers return the action to perform on the fault immediately, instead of having to call iommu_page_response with a crafted structure. Update IOMMU_PAGE_RESP* values to encompass most needs: - IOMMU_PAGE_RESP_HANDLED means "I took ownership of the fault and

[PATCH 05/37] iommu/sva: Track mm changes with an MMU notifier

When creating an io_mm structure, register an MMU notifier that informs us when the virtual address space changes and disappears. Add one new operation to the IOMMU driver: mm_invalidate is called when a range of addresses is unmapped, to let the IOMMU driver send ATC invalidations. Adding the

[PATCH 11/37] dt-bindings: document stall and PASID properties for IOMMU masters

On ARM systems, some platform devices behind an IOMMU may support stall and PASID features. Stall is the ability to recover from page faults and PASID offers multiple process address spaces to the device. Together they allow to do paging with a device. Let the firmware tell us when a device

[PATCH 08/37] iommu/fault: Handle mm faults

When a recoverable page fault is handled by the fault workqueue, find the associated mm and call handle_mm_fault. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/io-pgfault.c | 89 -- 1 file changed, 87

[PATCH 04/37] iommu/sva: Add a mm_exit callback for device drivers

When an mm exits, devices that were bound to it must stop performing DMA on its PASID. Let device drivers register a callback to be notified on mm exit. Add the callback to the iommu_param structure attached to struct device. Signed-off-by: Jean-Philippe Brucker

[PATCH 10/37] iommu/fault: Allow blocking fault handlers

Allow device driver to register their fault handler at different stages of the handling path. Since we now have a fault workqueue, it is easy to call their handler from blocking context. The API borrows "handler" and "thread" terms from the IRQ subsystem, even though they don't match exactly:

[PATCH 07/37] iommu: Add a page fault handler

Some systems allow devices to handle IOMMU translation faults in the core mm. For example systems supporting the PCI PRI extension or Arm SMMU stall model. Infrastructure for reporting such recoverable page faults was recently added to the IOMMU core, for SVA virtualization. Extend

[PATCH 03/37] iommu/sva: Manage process address spaces

Introduce boilerplate code for allocating IOMMU mm structures and binding them to devices. Four operations are added to IOMMU drivers: * mm_alloc(): to create an io_mm structure and perform architecture- specific operations required to grab the process (for instance on ARM, pin down the CPU

[PATCH 02/37] iommu/sva: Bind process address spaces to devices

Add bind() and unbind() operations to the IOMMU API. Device drivers can use them to share process page tables with their devices. bind_group() is provided for VFIO's convenience, as it needs to provide a coherent interface on containers. Other device drivers will most likely want to use

[PATCH 01/37] iommu: Introduce Shared Virtual Addressing API

Shared Virtual Addressing (SVA) provides a way for device drivers to bind process address spaces to devices. This requires the IOMMU to support the same page table format as CPUs, and requires the system to support I/O Page Faults (IOPF) and Process Address Space ID (PASID). When all of these are

[PATCH 00/37] Shared Virtual Addressing for the IOMMU

Shared Virtual Addressing (SVA) is the ability to share process address spaces with devices. It is called "SVM" (Shared Virtual Memory) by OpenCL and some IOMMU architectures, but since that abbreviation is already used for AMD virtualisation in Linux (Secure Virtual Machine), we prefer the less

[PATCHv2 5/6] iommu/intel: Rename dmar_fault() => dmar_serve_faults()

Fix the return value, parameters and a bit better naming. Signed-off-by: Dmitry Safonov --- drivers/iommu/dmar.c| 8 +++- drivers/iommu/intel-iommu.c | 2 +- drivers/iommu/intel_irq_remapping.c | 2 +- include/linux/dmar.h| 2 +- 4

[PATCHv2 4/6] iommu/intel: Handle DMAR faults on workqueue

dmar_fault() reports/handles/cleans DMAR faults in a cycle one-by-one. The nuisance is that it's set as a irq handler and runs with disabled interrupts - which works OK if you have only a couple of DMAR faults, but becomes a problem if your intel iommu has a plenty of mappings. We have a test

[PATCHv2 2/6] iommu/intel: Clean/document fault status flags

So one could decode them without opening the specification. Signed-off-by: Dmitry Safonov --- include/linux/intel-iommu.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index

[PATCHv2 3/6] iommu/intel: Introduce clear_primary_faults() helper

To my mind it's a bit more readable - and I will re-use it in the next patch. Signed-off-by: Dmitry Safonov --- drivers/iommu/dmar.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index

[PATCHv2 1/6] iommu/intel: Add __init for dmar_register_bus_notifier()

It's called only from intel_iommu_init(), which is init function. Signed-off-by: Dmitry Safonov --- drivers/iommu/dmar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 9a7ffd13c7f0..accf58388bdb 100644 ---

[PATCHv2 0/6] iommu/intel: Handle DMAR faults in a wq

Changes to v2: - Ratelimit printks for dmar faults (6 patch) First version: https://lkml.org/lkml/2018/1/24/364 A softlockup-panic fix I've meet on kernel test suite. While at it, fix a couple of minor issues. Cc: Alex Williamson Cc: David Woodhouse

Re: [PATCH] headers: untangle kmemleak.h from mm.h

Randy Dunlap writes: > From: Randy Dunlap > > Currently #includes for no obvious > reason. It looks like it's only a convenience, so remove kmemleak.h > from slab.h and add to any users of kmemleak_* > that don't already #include it. > Also