Prepare fault handling, probe and tlb sync functions to allow sharing
code between ARM SMMU driver and Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 53 +++--
drivers/iommu/arm-smmu.c| 42
Rearrange arm-smmu.c code into arm-smmu-common.h, arm-smmu-common.c
and arm-smmu.c.
This patch rearranges the arm-smmu.c code to allow sharing the ARM SMMU
driver code with dual ARM SMMU based Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 1922
NVIDIA's Xavier (Tegra194) SOC has three ARM SMMU(MMU-500) instances.
Two of the SMMU instances are used to interleave IOVA accesses across them.
The IOVA accesses from HW devices are interleaved across these two SMMU
instances
and they need to be programmed identical.
The existing ARM SMMU
Tegra194 SMMU driver supports Dual ARM SMMU configuration
supported in Tegra194 SOC.
The IOVA accesses from HW devices are interleaved across two
ARM SMMU devices.
Signed-off-by: Krishna Reddy
---
drivers/iommu/Makefile| 1 +
drivers/iommu/tegra194-smmu.c | 201
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Tuesday, October 23, 2018 2:57 PM
>
> Hi,
>
> On 10/22/18 6:22 PM, Raj, Ashok wrote:
> > On Mon, Oct 22, 2018 at 12:49:47PM +0800, Lu Baolu wrote:
> >> Hi,
> >>
> >> On 10/20/18 2:11 AM, Jean-Philippe Brucker wrote:
> >>> Some devices
> From: Raj, Ashok
> Sent: Wednesday, October 24, 2018 1:17 AM
>
> >
> > But that's not reason enough to completely disable PASID for the
> > device,
> > it could be the only one bound to that process, or PASID could be
> > only
> > used privately by the host device driver.
>
> Agree, there
On Mon, 2018-10-22 at 17:03 +0100, Jean-Philippe Brucker wrote:
> On 22/10/2018 11:07, Raj, Ashok wrote:
> > > For my own convenience I've been using the SVA infrastructure
> > > since
> > > I already had the locking and IOMMU ops in place. The
> > > proposed
> > > interface is also
On 2018/10/23 03:29, Konrad Rzeszutek Wilk wrote:
> On Sat, Sep 22, 2018 at 08:56:58PM +0800, He Zhe wrote:
>> May I have your input?
> Alternatively would it make more sense for it to assume some default
> value?
Maybe, but the original code has no default value and I have no idea
what default
Hi Robin,
On Tue, Sep 25, 2018 at 6:01 PM Robin Murphy wrote:
>
> On 10/09/18 07:25, Vivek Gautam wrote:
> > Qcom's implementation of arm,mmu-500 require to serialize all
> > TLB invalidations for context banks.
>
> What does "serailize all TLB invalidations" actually mean, because it's
> not
Hi,
On 10/22/18 6:22 PM, Raj, Ashok wrote:
On Mon, Oct 22, 2018 at 12:49:47PM +0800, Lu Baolu wrote:
Hi,
On 10/20/18 2:11 AM, Jean-Philippe Brucker wrote:
Some devices might support multiple DMA address spaces, in particular
those that have the PCI PASID feature. PASID (Process Address Space
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