Hey Tom,
On Fri, Aug 09, 2019 at 04:50:48PM +, Lendacky, Thomas wrote:
> On 8/9/19 10:22 AM, Joerg Roedel wrote:
> > + if ((iommu_def_domain_type == IOMMU_DOMAIN_IDENTITY) &&
> > + sme_active()) {
> > + pr_info("SME detected - Disabling default IOMMU passthrough\n");
> > +
...and of course I had to forget someone's cc - sorry Jordan! :(
Robin.
On 09/08/2019 18:07, Robin Murphy wrote:
Hi all,
This is a big refactoring of arm-smmu in order to help cope with the
various divergent implementation details currently flying around. So
far we've been accruing various
Allocating and initialising a context for a domain is another point
where certain implementations are known to want special behaviour.
Currently the other half of the Cavium workaround comes into play here,
so let's finish the job to get the whole thing right out of the way.
Signed-off-by: Robin
Reset is an activity rife with implementation-defined poking. Add a
corresponding hook, and use it to encapsulate the existing MMU-500
details.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c | 49 +++
drivers/iommu/arm-smmu.c | 39
Clean up the remaining accesses to GR0 registers, so that everything is
now neatly abstracted. This folds up the Non-Secure alias quirk as the
first step towards moving it out of the way entirely. Although GR0 does
technically contain some 64-bit registers (sGFAR and the weird SMMUv2
HYPC and MONC
Probing the ID registers and setting up the SMMU configuration is an
area where overrides and workarounds may well be needed. Indeed, the
Cavium workaround detection lives there at the moment, so let's break
that out.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-impl.c | 24
Add some nascent infrastructure for handling implementation-specific
details outside the flow of the architectural code. This will allow us
to keep mutually-incompatible vendor-specific hooks in their own files
where the respective interested parties can maintain them with minimal
chance of
We're about to start using it for more than just register definitions,
so generalise the name.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 2 +-
drivers/iommu/{arm-smmu-regs.h => arm-smmu.h} | 6 +++---
drivers/iommu/qcom_iommu.c| 2 +-
3
Move detection of the Secure access quirk to its new home, trimming it
down in the process - time has proven that boolean DT flags are neither
ideal nor necessarily sufficient, so it's highly unlikely we'll ever add
more, let alone enough to justify the frankly overengineered parsing
machinery.
Context bank accesses are fiddly enough to deserve a number of extra
helpers to keep the callsites looking sane, even though there are only
one or two of each.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 137 ---
1 file changed, 72
To keep register-access quirks manageable, we want to structure things
to avoid needing too many individual overrides. It seems fairly clean to
have a single interface which handles both global and context registers
in terms of the architectural pages, so the first preparatory step is to
rework
Since we now use separate iommu_gather_ops for stage 1 and stage 2
contexts, we may as well divide up the monolithic callback into its
respective stage 1 and stage 2 parts.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 66 ++--
1 file changed, 37
The smmu_write_atomic_lq oddity made some sense when the context
format was effectively tied to CONFIG_64BIT, but these days it's
simpler to just pick an explicit access size based on the format
for the one-and-a-half times we actually care.
Signed-off-by: Robin Murphy
---
Introduce some register access abstractions which we will later use to
encapsulate various quirks. GR1 is the easiest page to start with.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git
FIELD_PREP remains a terrible name, but the overall simplification will
make further work on this stuff that much more manageable. This also
serves as an audit of the header, wherein we can impose a consistent
grouping and ordering of the offset and field definitions
Signed-off-by: Robin Murphy
As for GR0, use the bitfield helpers to make GR1 usage a little cleaner,
and use it as an opportunity to audit and tidy the definitions. This
tweaks the handling of CBAR types to match what we did for S2CR a while
back, and fixes a couple of names which didn't quite match the latest
architecture
Hi all,
This is a big refactoring of arm-smmu in order to help cope with the
various divergent implementation details currently flying around. So
far we've been accruing various quirks and errata workarounds within
the main flow of the driver, but given that it's written to an
architecture rather
Finish the final part of the job, once again updating some names to
match the current spec.
Signed-off-by: Robin Murphy
---
drivers/iommu/arm-smmu-regs.h | 86 ++-
drivers/iommu/arm-smmu.c | 16 +++
drivers/iommu/qcom_iommu.c| 13 +++---
3 files
On 8/9/19 10:22 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Using Passthrough mode when SME is active causes certain
> devices to use the SWIOTLB bounce buffer. The bounce buffer
> code has an upper limit of 256kb for the size of DMA
> allocations, which is too small for certain devices and
On 8/9/19 11:13 AM, Joerg Roedel wrote:
> On Wed, Aug 07, 2019 at 11:26:50AM +0300, Tero Kristo wrote:
>> +static inline int omap_iommu_domain_deactivate(struct iommu_domain *domain)
>> {}
>> +static inline int omap_iommu_domain_activate(struct iommu_domain *domain) {}
>
> This caused
On Wed, Aug 07, 2019 at 11:26:50AM +0300, Tero Kristo wrote:
> +static inline int omap_iommu_domain_deactivate(struct iommu_domain *domain)
> {}
> +static inline int omap_iommu_domain_activate(struct iommu_domain *domain) {}
This caused compilation warnings, I queued the fix below.
>From
m...@ellerman.id.au writes:
> Thiago Jung Bauermann writes:
>> Hello,
>>
>> This version has only a small change in the last patch as requested by
>> Christoph and Halil, and collects Reviewed-by's.
>>
>> These patches are applied on top of v5.3-rc2.
>>
>> I don't have a way to test SME, SEV,
On Thu, Aug 08, 2019 at 06:17:07PM +0800, Kai-Heng Feng wrote:
> Raven Ridge systems may have malfunction touchpad or hang at boot if
> incorrect IVRS IOAPIC is provided by BIOS.
>
> Users already found correct "ivrs_ioapic=" values, let's put them inside
> kernel to workaround buggy BIOS.
Will
On Wed, Aug 07, 2019 at 11:26:44AM +0300, Tero Kristo wrote:
> Here are a few fixes for OMAP IOMMU. These are mostly towards getting
> runtime PM support functional again for the IOMMU.
Applied all, thanks.
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On Tue, Aug 06, 2019 at 08:14:08AM +0800, Lu Baolu wrote:
> drivers/iommu/intel-iommu.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Applied to iommu/fixes, thanks.
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On Tue, Aug 06, 2019 at 06:11:51PM -0700, Nicolin Chen wrote:
> Well..it was triggered in our downstream test that's supposed to
> cover large size (> 4G) corner case, so I don't feel it's "easy"
> but our test case was running with 4.14 kernel so I also feel it
> might be a good idea to Cc stable
On Tue, Jul 23, 2019 at 07:00:37PM +, Suthikulpanit, Suravee wrote:
> Re-factore the logic for activate/deactivate guest virtual APIC mode (GAM)
> into helper functions, and export them for other drivers (e.g. SVM).
> to support run-time activate/deactivate of SVM AVIC.
>
> Cc: Joerg Roedel
On Sat, Jul 20, 2019 at 10:01:26AM +0800, Lu Baolu wrote:
> drivers/iommu/intel-iommu-debugfs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
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Hi,
here is a small patch-set to disable IOMMU Passthrough mode when SME is
active even when CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y is set.
The reason for that change is that SME with passthrough mode turned out
to be fragile with devices requiring SWIOTLB, mainly because SWIOTLB has
a maximum
From: Joerg Roedel
Introduce a subsys_initcall for IOMMU code and use it to
print the default domain type at boot.
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/iommu.c
From: Joerg Roedel
Set the default domain-type at runtime, not at compile-time.
This keeps default domain type setting in one place when we
have to change it at runtime.
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
From: Joerg Roedel
Using Passthrough mode when SME is active causes certain
devices to use the SWIOTLB bounce buffer. The bounce buffer
code has an upper limit of 256kb for the size of DMA
allocations, which is too small for certain devices and
causes them to fail.
With this patch we enable
Thiago Jung Bauermann writes:
> Hello,
>
> This version has only a small change in the last patch as requested by
> Christoph and Halil, and collects Reviewed-by's.
>
> These patches are applied on top of v5.3-rc2.
>
> I don't have a way to test SME, SEV, nor s390's PEF so the patches have only
>
On 08.08.2019 19:00, Christoph Hellwig wrote:
Ther is no need to go through dma_common_mmap for the arm-nommu
There. :-)
dma mmap implementation as the only possible memory not handled above
could be that from the per-device coherent pool.
Signed-off-by: Christoph Hellwig
[...]
MBR,
Hi Christoph,
On Thu, Aug 8, 2019 at 6:01 PM Christoph Hellwig wrote:
> CONFIG_ARCH_NO_COHERENT_DMA_MMAP is now functionally identical to
> !CONFIG_MMU, so remove the separate symbol. The only difference is that
> arm did not set it for !CONFIG_MMU, but arm uses a separate dma mapping
>
The commit 72921427d46b
("string.h: Add str_has_prefix() helper function")
introduced str_has_prefix() to substitute error-prone
strncmp(str, const, len).
strncmp(str, const, len) is easy to have error in len
because of counting error or sizeof(const) without - 1.
These patches replace such
strncmp(str, const, len) is error-prone because len
is easy to have typo.
The example is the hard-coded len has counting error
or sizeof(const) forgets - 1.
So we prefer using newly introduced str_has_prefix()
to substitute such strncmp to make code better.
Signed-off-by: Chuhong Yuan
---
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