Re: [PATCH v4 0/7] Use 1st-level for IOVA translation

2019-12-20 Thread Lu Baolu
Hi again, On 2019/12/20 19:50, Liu, Yi L wrote: 3) Per VT-d spec, FLPT has canonical requirement to the input addresses. So I'd suggest to add some enhance regards to it. Please refer to chapter 3.6:-). 3.6 First-Level Translation First-level translation restricts the input-address to a canonic

Re: [PATCH v4 0/7] Use 1st-level for IOVA translation

2019-12-20 Thread Lu Baolu
Hi Yi, Thanks for the comments. On 12/20/19 7:50 PM, Liu, Yi L wrote: Hi Baolu, In a brief, this version is pretty good to me. However, I still want to have the following checks to see if anything missed. Wish it helps. 1) would using IOVA over FLPT default on? My opinion is that before we ha

Re: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level

2019-12-20 Thread Lu Baolu
Hi Yi, On 12/20/19 7:44 PM, Liu, Yi L wrote: From: Lu Baolu [mailto:baolu...@linux.intel.com] Sent: Thursday, December 19, 2019 11:17 AM To: Joerg Roedel ; David Woodhouse ; Alex Williamson Subject: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level Intel VT-d in scalabl

Re: [Freedreno] [PATCH 5/5] drm/msm/a6xx: Add support for using system cache(LLC)

2019-12-20 Thread Jordan Crouse
On Fri, Dec 20, 2019 at 03:40:59PM +0530, smase...@codeaurora.org wrote: > On 2019-12-20 01:28, Jordan Crouse wrote: > >On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote: > >>The last level system cache can be partitioned to 32 different slices > >>of which GPU has two slices prealloca

Re: [RFC 00/13] virtio-iommu on non-devicetree platforms

2019-12-20 Thread Jacob Pan (Jun)
On Wed, 18 Dec 2019 12:20:44 +0100 Jean-Philippe Brucker wrote: > On Tue, Dec 03, 2019 at 07:01:36PM -0800, Jacob Pan (Jun) wrote: > > Hi Jean, > > > > Sorry for the delay, I was out last week. Comments inline below. > > > > On Mon, 25 Nov 2019 19:02:47 +0100 > > Jean-Philippe Brucker wrote: >

Re: [git pull] IOMMU Fixes for Linux v5.5-rc2

2019-12-20 Thread pr-tracker-bot
The pull request you sent on Fri, 20 Dec 2019 12:30:26 +0100: > git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git > tags/iommu-fixes-v5.5-rc2 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/b371ddb94fae82b6565020639b7db31934043c65 Thank you! -- Deet-doot-

Re: [PATCH v4 00/16] iommu: Permit modular builds of ARM SMMU[v3] drivers

2019-12-20 Thread Joerg Roedel
On Thu, Dec 19, 2019 at 12:03:36PM +, Will Deacon wrote: > Ard Biesheuvel (1): > iommu/arm-smmu: Support SMMU module probing from the IORT > > Greg Kroah-Hartman (1): > PCI/ATS: Restore EXPORT_SYMBOL_GPL() for pci_{enable,disable}_ats() > > Will Deacon (14): > drivers/iommu: Export core

Re: [PATCH v4 03/16] PCI/ATS: Restore EXPORT_SYMBOL_GPL() for pci_{enable,disable}_ats()

2019-12-20 Thread Bjorn Helgaas
On Fri, Dec 20, 2019 at 09:43:03AM +0100, Joerg Roedel wrote: > Hi Bjorn, > > On Thu, Dec 19, 2019 at 12:03:39PM +, Will Deacon wrote: > > From: Greg Kroah-Hartman > > > > Commit d355bb209783 ("PCI/ATS: Remove unnecessary EXPORT_SYMBOL_GPL()") > > unexported a bunch of symbols from the PCI c

RE: [PATCH v4 0/7] Use 1st-level for IOVA translation

2019-12-20 Thread Liu, Yi L
Hi Baolu, In a brief, this version is pretty good to me. However, I still want to have the following checks to see if anything missed. Wish it helps. 1) would using IOVA over FLPT default on? My opinion is that before we have got gIOVA nested translation done for passthru devices, we should make

RE: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level

2019-12-20 Thread Liu, Yi L
> From: Lu Baolu [mailto:baolu...@linux.intel.com] > Sent: Thursday, December 19, 2019 11:17 AM > To: Joerg Roedel ; David Woodhouse ; > Alex Williamson > Subject: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first > level > > Intel VT-d in scalable mode supports two types of pag

[git pull] IOMMU Fixes for Linux v5.5-rc2

2019-12-20 Thread Joerg Roedel
Hi Linus, thanks for taking care of the KASAN related IOMMU fix while I was dived into other development work and sorry for the inconvenience. Here are the other IOMMU fixes that piled up during the last weeks: The following changes since commit d1eef1c619749b2a57e514a3fa67d9a516ffa919: Linux

Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779

2019-12-20 Thread chao hao
On Mon, 2019-12-16 at 20:05 +0800, Yong Wu wrote: > On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > > This patch adds description for MT6779 IOMMU. > > > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > > use ARM Short-Descriptor translation format. > > > > The MT6779 IOMMU h

Re: [PATCH 5/5] drm/msm/a6xx: Add support for using system cache(LLC)

2019-12-20 Thread smasetty
On 2019-12-20 01:28, Jordan Crouse wrote: On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote: The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for cac

Re: [PATCH] iommu/vt-d: Don't reject nvme host due to scope mismatch

2019-12-20 Thread Jerry Snitselaar
On Fri Dec 20 19, jimyan wrote: On a system with an Intel PCIe port configured as a nvme host device, iommu initialization fails with DMAR: Device scope type does not match for :80:00.0 This is because the DMAR table reports this device as having scope 2 (ACPI_DMAR_SCOPE_TYPE_BRIDGE):

Re: [PATCH v4 03/16] PCI/ATS: Restore EXPORT_SYMBOL_GPL() for pci_{enable,disable}_ats()

2019-12-20 Thread Joerg Roedel
Hi Bjorn, On Thu, Dec 19, 2019 at 12:03:39PM +, Will Deacon wrote: > From: Greg Kroah-Hartman > > Commit d355bb209783 ("PCI/ATS: Remove unnecessary EXPORT_SYMBOL_GPL()") > unexported a bunch of symbols from the PCI core since the only external > users were non-modular IOMMU drivers. Although