Hi Joerg,
On 1/17/20 6:21 PM, Joerg Roedel wrote:
On Wed, Jan 01, 2020 at 01:26:47PM +0800, Lu Baolu wrote:
This splits iommu group allocation from adding devices. This makes
it possible to determine the default domain type for each group as
all devices belonging to the group have been determin
Hi Joerg,
On 1/17/20 5:59 PM, Joerg Roedel wrote:
On Thu, Jan 16, 2020 at 09:52:36AM +0800, Lu Baolu wrote:
Address field in device TLB invalidation descriptor is qualified
by the S field. If S field is zero, a single page at page address
specified by address [63:12] is requested to be invalida
Hi Bjorn,
On 1/18/20 8:18 AM, Bjorn Helgaas wrote:
On Wed, Jan 01, 2020 at 01:26:46PM +0800, Lu Baolu wrote:
The new parameter takes a list of devices separated by a semicolon.
Each device specified will have its iommu_passthrough bit in struct
device set. This is very similar to the existing '
On Wed, Jan 01, 2020 at 01:26:46PM +0800, Lu Baolu wrote:
> The new parameter takes a list of devices separated by a semicolon.
> Each device specified will have its iommu_passthrough bit in struct
> device set. This is very similar to the existing 'disable_acs_redir'
> parameter.
>
> Signed-off-b
This removes the sanity check required for VMD child devices. The new
pci_real_dma_dev() DMA alias mechanism places them in the same IOMMU
group as the VMD endpoint. Assignment of the group would require
assigning the VMD endpoint, where unbinding the VMD endpoint removes the
child device domain fr
The PCI device may have a DMA requester on another bus, such as VMD
subdevices needing to use the VMD endpoint. This case requires the real
DMA device when mapping to IOMMU.
Signed-off-by: Jon Derrick
---
drivers/iommu/intel-iommu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/dr
The current DMA alias implementation requires the aliased device be on
the same PCI bus as the requester ID. This introduces an arch-specific
mechanism to point to another PCI device when doing mapping and
PCI DMA alias search. The default case returns the actual device.
CC: Christoph Hellwig
Sig
To be used by Intel-IOMMU code to find the correct domain.
CC: Christoph Hellwig
Signed-off-by: Jon Derrick
---
arch/x86/include/asm/pci.h | 4 ++--
drivers/pci/controller/vmd.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/includ
From: Christoph Hellwig
Various helpers need the pci_sysdata just to dereference a single field
in it. Add a little helper that returns the properly typed sysdata
pointer to require a little less boilerplate code.
Signed-off-by: Christoph Hellwig
[jonathan.derrick: to_pci_sysdata const argumen
Devices on the VMD domain use the VMD endpoint's requester ID and have
been relying on the VMD endpoint's DMA operations. The problem with this
was that VMD domain devices would use the VMD endpoint's attributes when
doing DMA and IOMMU mapping. We can be smarter about this by only using
the VMD en
From: Christoph Hellwig
There are no users of X86_DEV_DMA_OPS left, so remove the code.
Reviewed-by: Jon Derrick
Signed-off-by: Christoph Hellwig
---
arch/x86/Kconfig | 3 ---
arch/x86/include/asm/device.h | 10 --
arch/x86/pci/common.c | 38 -
v3 Set:
https://lore.kernel.org/linux-iommu/20200113181742.ga27...@e121166-lin.cambridge.arm.com/T/#t
v2 Set:
https://lore.kernel.org/linux-iommu/1578580256-3483-1-git-send-email-jonathan.derr...@intel.com/T/#t
v1 Set:
https://lore.kernel.org/linux-iommu/20200107134125.gd30...@8bytes.org/T/#t
V
Arm SMMUv3.2 adds support for TLB range invalidate operations.
Support for range invalidate is determined by the RIL bit in the IDR3
register.
The range invalidate is in units of the leaf page size and operates on
1-32 chunks of a power of 2 multiple pages. First, we determine from the
size what p
On Tue, 2020-01-14 at 09:54 +0100, Christoph Hellwig wrote:
> On Fri, Jan 10, 2020 at 10:21:12AM -0700, Jon Derrick wrote:
> > Devices on the VMD domain use the VMD endpoint's requester ID and have
> > been relying on the VMD endpoint's DMA operations. The problem with this
> > was that VMD domain
On 12/31/19 7:54 PM, David Rientjes wrote:
> Christoph, Thomas, is something like this (without the diagnosic
> information included in this patch) acceptable for these allocations?
> Adding expansion support when the pool is half depleted wouldn't be *that*
> hard.
Sorry for the delay in resp
On Thu, 2020-01-16 at 09:44 -0800, Christoph Hellwig wrote:
> Hi Abdul,
>
> I think the problem is that mpt3sas has some convoluted logic to do
> some DMA allocations with a 32-bit coherent mask, and then switches
> to a 63 or 64 bit mask, which is not supported by the DMA API.
>
> Can you try th
On Wed, Jan 01, 2020 at 01:26:47PM +0800, Lu Baolu wrote:
> This splits iommu group allocation from adding devices. This makes
> it possible to determine the default domain type for each group as
> all devices belonging to the group have been determined.
I think its better to keep group allocation
Adding Suravee, who wrote the IOMMU Perf Counter code.
On Tue, Jan 14, 2020 at 08:12:20AM -0700, Shuah Khan wrote:
> init_iommu_perf_ctr() clobbers the register when it checks write access
> to IOMMU perf counters and fails to restore when they are writable.
>
> Add save and restore to fix it.
>
On Thu, Jan 09, 2020 at 11:02:49AM +0800, Adrian Huang wrote:
> This series optimizes the register reading by using readq instead of
> readl and cleans up the unused variables.
>
> Adrian Huang (2):
> iommu/amd: Replace two consecutive readl calls with one readq
> iommu/amd: Remove unused stru
On Thu, Jan 16, 2020 at 10:25:49AM +, Will Deacon wrote:
> Hi Joerg,
>
> Please pull these Arm SMMU updates for 5.6. The branch is based on your
> arm/smmu branch and includes a patch addressing the feedback from Greg
> about setting the module 'owner' field in the 'iommu_ops'.
>
> I've used
On Thu, Jan 16, 2020 at 09:52:36AM +0800, Lu Baolu wrote:
> Address field in device TLB invalidation descriptor is qualified
> by the S field. If S field is zero, a single page at page address
> specified by address [63:12] is requested to be invalidated. If S
> field is set, the least significant
On Wed, Jan 15, 2020 at 11:03:54AM +0800, Lu Baolu wrote:
> Barret Rhoden (2):
> iommu/vt-d: Mark firmware tainted if RMRR fails sanity check
> iommu/vt-d: Add RMRR base and end addresses sanity check
>
> Lu Baolu (2):
> iommu/vt-d: Allow devices with RMRRs to use identity domain
> iommu/v
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