Suravee Suthikulpanit @ 2020-10-14 19:50 MST:
> Certain device drivers allocate IO queues on a per-cpu basis.
> On AMD EPYC platform, which can support up-to 256 cpu threads,
> this can exceed the current MAX_IRQ_PER_TABLE limit of 256,
> and result in the error message:
>
> AMD-Vi: Failed t
On Tue, 17 Nov 2020 18:25:30 +0800, John Garry wrote:
> This series contains a patch to solve the longterm IOVA issue which
> leizhen originally tried to address at [0].
>
> A sieved kernel log is at the following, showing periodic dumps of IOVA
> sizes, per CPU and per depot bin, per IOVA size gr
On Tue, Dec 01, 2020 at 03:35:02PM +, John Garry wrote:
> On 17/11/2020 10:25, John Garry wrote:
> Is there any chance that we can get these picked up for 5.11? We've seen
> this issue solved here for a long time.
>
> Or, @Robin, let me know if not happy with this since v1.
>
> BTW, patch #4
On Tue, Nov 24, 2020 at 11:46:22PM +, Ashish Kalra wrote:
> Hello Konrad,
>
> On Mon, Nov 23, 2020 at 10:56:31PM +, Ashish Kalra wrote:
> > Hello Konrad,
> >
> > On Mon, Nov 23, 2020 at 12:56:32PM -0500, Konrad Rzeszutek Wilk wrote:
> > > On Mon, Nov 23, 2020 at 06:06:47PM +0100, Borisla
On 17/11/2020 10:25, John Garry wrote:
Hi Will,
Is there any chance that we can get these picked up for 5.11? We've seen
this issue solved here for a long time.
Or, @Robin, let me know if not happy with this since v1.
BTW, patch #4 has been on the go for ~1 year now, and is a nice small
opt
Hi Eric
On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote:
>@@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
>* insertion to guarantee those are observed before the TLBI. Do be
>* careful, 007.
>*/
>- if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)
Hi Eric
On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote:
>@@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
> * insertion to guarantee those are observed before the TLBI. Do be
> * careful, 007.
> */
>- if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
On Tue, 1 Dec 2020 09:31:48 +0800, Lu Baolu wrote:
> Below patch is ready for v5.11. It includes:
>
> - Avoid GFP_ATOMIC where it is not needed
>
> Can you please consider it for v5.11?
>
> Best regards,
> Lu Baolu
>
> [...]
Applied to arm64 (for-next/iommu/vt-d), thanks!
[1/1] iommu/vt-d: A
On Tue, Dec 01, 2020 at 12:36:58PM +0900, Sergey Senozhatsky wrote:
> Not that I have any sound experience in this area, but the helper
> probably won't hurt. Do you also plan to add vmap() to that helper
> or dma_alloc_noncontiguous()/sg_alloc_table_from_pages() only?
Yes, I think adding the vmap
Hi Xingang,
On 12/1/20 2:33 PM, Xingang Wang wrote:
> Hi Eric
>
> On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote:
>> @@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
>> * insertion to guarantee those are observed before the TLBI. Do be
>> * careful, 007.
>>
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